DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/13/26 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13-18 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. (Note: rejection applies to subsequent dependent claims).
The claim limitation “wherein each of the plurality of data driving integrated circuits comprises: a first communication circuit which sends first data and first verification data for the first data at a first data rate via a first communication line; and a second communication circuit which sends second data including image data for driving pixels on a display panel via the first communication line at a second data rate which is higher than the first data rate, and sends second verification data corresponding to the first verification data at the second data rate” is not described in the specification as filed.
The specification as filed describes where the data processing device (not the data driving integrated circuit) includes a first communication circuit that sends first data and first verification data for the first data and a second communication circuit that sends second data including image data and second verification data corresponding to the first verification data.
{Examiner Note: for purposes of examination this limitation will be read “A display driving device comprising a data processing device, wherein the data processing device comprises: …”}.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7, 13-14, 19 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US 2021/0406108) in view of Suh et al. (US 2009/0172224).
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
As to Claim 1, Kim et al. discloses A display driving device comprising a plurality of data driving integrated circuits, wherein each of the plurality of data driving integrated circuits (fig.2-3) comprises:
a first communication circuit which receives first data at a first data rate via a first communication line and determines whether the first data has an error according to a first rule (fig.3, para.0103; data driving device 130 includes communication circuit 334 that receives configuration value data and the error detection information via low speed communication through communication lines ML; para.0103);
a second communication circuit which receives second data via the first communication line at a second data rate which is higher than the first data rate, and which determines whether the second data has an error according to a second rule which is different from the first rule (fig.3,9, para.0120; communication circuit 334 receive the clock pattern, the image data, and error detection information high speed communication through communication lines ML and determine if an error has occurred); and
a circuit that controls pixels on a display panel to be driven in accordance with image data included in the second data (fig.2-3, 9; para.0060-0062, 0120-0121).
Kim et al. discloses where the first communication circuit receives first data and the second data via the communication line ML. Kim et al. does not expressly disclose the first communication circuit determines whether the first data has an error according to a first rule; and where the second data is received by a second communication circuit, and second rule which is different from the first rule.
Suh et al. discloses a display device comprising data receiver that includes a first communication circuit that receives first data at a first data rate and determines whether the first data has an error according to a first rule (fig.3b, para.0096-0097,0100; low speed reception unit 360 receives secondary data which may include ECC or CRC information, and is transmitted to error checking unit 390 to check an error occurs in transmission), and a second communication circuit receives second data at a second data rate (fig.3b, para.0094-0095, 0100 high speed reception unit 350 receives primary data that includes ECC or CRC and error checking unit 390 checks if error occurs in transmission), where second rule which is different from the first rule (para.0095,0097,0100,0103, data may be checked using ECC or CRC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al. with the teachings of Suh et al., such that the first data (of Kim) is received by a first communication circuit and checked for errors using ECC or CRC and the second data (of Kim) is received by a second communication circuit and checked for error using ECC or CRC (high-speed reception unit/error checking unit of Suh). The motivation being to reduce reception errors of data and enhance a data processing efficiency.
As to Claim 4, Kim et al. in view of Suh et al. disclose wherein, upon finding an error in a process of decoding the second data, the second communication circuit determines that the second data is erroneous data (Kim-fig.9, para.0120; Suh-para.0100).
As to Claim 5, Kim et al. in view of Suh et al. disclose, wherein the first communication circuit determines whether the first data has an error by checking a CRC (cyclical redundancy check) value (Suh-para. 0096-0097,0100).
As to Claim 7, Kim et al. in view of Suh et al disclose: wherein the second communication circuit trains a communication clock at the second data rate by receiving a clock training signal, and determines whether there is a communication error by checking what clock training pattern the clock training signal has after completion of the training (Kim-para.0058-0059,0076,0127-0128).
As to Claim 13, Kim et al. discloses A display driving device comprising a data processing device [a plurality of data driving integrated circuits], (fig.2-3),
wherein the data processing device [each of the plurality of data driving integrated circuits] comprises: a first communication circuit which sends first data and first verification data for the first data at a first data rate via a first communication line (fig.3, para.0103,0116; communication circuit 344 sends configuration value data, error detection information through low speed communication via communication line ML); and
a second communication circuit which sends second data including image data for driving pixels on a display panel via the first communication line at a second data rate which is higher than the first data rate, and sends second verification data corresponding to the first verification data at the second data rate (fig.3, para.0103, 0119; communication circuit 344 sends clock pattern, the image data, and error detection information through high speed communication via communication line ML; para.0119-error detection information received through high-speed communication is compared with error detection information received during low-speed communication to determine whether an error has occurred).
Kim et al. does not expressly disclose where the second data is sent by “a second communication circuit…”
Suh et al. discloses a transmitter (fig.2-3a), comprising a second communication circuit which sends second data including image data (fig.3a, para.0082; high speed transmission unit 340 sends image data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Kim et al. with the teachings of Suh et al., such that the first data (of Kim) is transmitted by a first communication circuit and the second data (of Kim) is transmitted by a second communication circuit. The motivation being to reduce transmission errors of data and enhance a data processing efficiency.
As to Claim 14, Kim et al. in view of Suh et al. disclose wherein the first verification data includes a CRC (cyclical redundancy check) value for the first data (Kim-para. 0116,0120,0126; Suh-para.0082, 0085), and the second verification data includes a CRC comparison value corresponding to the CRC check value (Kim-para.0116,0120,0126; Suh-para.0082,0085).
As to Claim 19 is a method claim drawn to the apparatus of Claim 1 and is rejected for the same reasons as set forth above
Claim 2 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US 2021/0406108) in view of Suh et al. (US 2009/0172224), further in view of in view of Minagawa et al. (US 2012/0201309).
As to Claim 2, Kim et al. in view of Suh et al. do not expressly disclose, but Minagawa et al. discloses: wherein the second data comprises a plurality of unit data, and the second communication circuit decodes each of the plurality unit data according to a decoding table, and, upon finding out that the unit data a unit of data included in the second data is not included in the decoding table, determines that the second data is erroneous data. (para.0033- 0034; if a code word in the bitstream is not matched to an entry in the VLC table, then an error is indicated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al.,, such that second data is encoded with a variable length code, as disclosed by Minagawa et al, the motivation being to enable code error detection from a variable length code table and distribution of decoded data, thereby reducing processor load and time to detect an error for decoded image data.
Claim 3 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US 2021/0406108) in view of Suh et al. (US 2009/0172224), further in view of in view of Gauvin et al. (US 2014/0223270).
As to Claim 3, Kim et al. in view of Suh et al, do not expressly disclose, but Gauvin et al. discloses: wherein, upon finding out that the second data which is encoded by LRLC (Limited Run Length Code) has a run length that exceeds a reference value, the second communication circuit determines that the second data is erroneous data (fig.3; para.0020, 0023).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al., with the teachings of Gauvin et al., the motivation being to provide classification of bit errors in run length limited data transmitted over a channel.
Claim 9-10, 17 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US 2021/0406108) in view of Suh et al. (US 2009/0172224), further in view of in view of Lee et al. (US 2015/0154943).
As to Claim 9, Kim et al. in view of Suh et al. do not expressly disclose, but Lee et al. discloses: wherein the second communication circuit evaluates communication performance through a BER (Bit Error Rate) test pattern received at the second data rate (para.0046, 0061,0070, 0139,0141).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al, with the teachings of Lee et al., the motivation being to detect transmission errors and improve test efficiency.
As to Claim 10, Kim et al. in view of Suh et al., as modified by Lee et al., disclose wherein the first communication circuit receives a setting value for a BER test at the first data rate (Lee para.0046, 0061, 0070, 0137, 0139, 0141-0143).
As to Claim 17, Kim et al. in view of Suh et al. do not expressly disclose, but Lee et al. discloses: wherein the first communication circuit sends a setting value for a BER (Bit Error Rate) test at the first data rate, and the second communication circuit sends a BER test pattern at the second data rate (fig.21, BERT mode (read as setting value) a test pattern is generated sent to timing controller embedded S-IC; para.0139,0141-0143).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al, with the teachings of Lee et al., the motivation being to detect transmission errors and improve test efficiency.
Claim 11-12, 18 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US 2021/0406108) in view of Suh et al. (US 2009/0172224), further in view of Alrod et al. (US 2017/0269839).
As to Claim 11, Kim et al. in view of Suh et al. do not expressly disclose, but Alrod et al. discloses: wherein the second communication circuit matches a value of M bits to a symbol consisting of N bits and includes the symbol in the second data when sending the second data, where M is a natural number and N is a natural number greater than M (fig.1, para.0012, 0015, 0028, 0034, 0036, 0062,0072,0118; received data 180 having one or more n-tuples and is mapped to m-tuple of deshaped data 182, where m<n).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al., with the teachings of Alrod et al., the motivation being to reduce wear to the memory and enable compensation for one or more bit errors during decoding of transformed data.
As to Claim 12, Kim et al. in view of Suh et al., as modified by Alrod et al. disclose wherein the second communication circuit corrects an error in a bit included in one symbol by using another symbol received before or after the one symbol (Alrod-para.0034, 0037, 0060, 0062, 0068, 0120).
As to Claim 18, Kim et al. in view of Suh et al., do not expressly disclose, but Alrod et al. discloses: wherein the second communication circuit matches a value of M bits to a symbol consisting of N bits and includes the symbol in the second data when sending the second data, where M is a natural number and N is a natural number greater than M (fig.1, para.0014,0023,0026-0027,0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al., with the teachings of Alrod et al., the motivation being to reduce wear to the memory and enable compensation for one or more bit errors during decoding of transformed data.
Claim 16 is/are rejected under 35 U.S.C. 103 as being obvious over Kim et al. (US 2021/0406108) in view of Suh et al. (US 2009/0172224), further in view of Kim et al. (US 2019/0103070, hereinafter Kim070).
As to Claim 16, Kim et al. in view of Suh et al., do not expressly disclose but Kim070 discloses: wherein the second communication circuit encodes the second data by an LRLC (Limited Run Length Coding) method according to a predetermined encoding table (fig.4, 6; para.0075-0076,0090-0094).
It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device disclosed by Kim et al. in view of Suh et al., with teachings of Kim070, the motivation being prevent data of a packet from being affected by a jitter in a transmission process of the packet, so that it is possible to implement a high speed interface between a data transmission apparatus and a data reception apparatus.
Allowable Subject Matter
Claims 6, 8, 15, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Conclusion
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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