DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/27/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 9-10, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0154943) in view of Oh et al. (US 2016/0133178), further in view of Lin et al. (US 2009/0096775), and further in view of Yang et al. (US 2014/0049524).
As to Claim 1, Lee et al. discloses A display driving device comprising: a first communication circuit which receives first data at a first data rate via a first communication line (fig.3-6; source driver 420 receives data packet main link) and determines whether the first data has an error according to a first rule (fig.3-6; para.0067-0074 source driver 420 includes error detection that includes an counter 425 and CRC decoder, which detects error occurrence in the display data; para.0105),
a second communication circuit which receives second data via the first communication line at a second data rate which is higher than the first data rate (fig.3-6; source driver 430 receives data packet main link, where pieces of display data provided to the source drivers may be different from each other; para.0073), and which determines whether the second data has an error according to a second rule which is different from the first rule (fig.3-6; para.0067-0074 source driver 430 includes error detection unit including an counter 425 that detects error occurrence in the display data; para.0105); and
a circuit that controls pixels on a display panel to be driven in accordance with image data included in the second data (fig.11-14, para.0101-0102, the timing controller may receive test results from the source drivers (which includes display data corresponding to second data of second source driver) and the control unit 616 displays the test results on a panel of the display along with display data; fig.15-16B- para.0112, 0115, data control unit may only display the test results; fig.17- para.0119-0121; fig.18B- when an error counting result of the source driver is greater than a target value, the environment configuration data of the source driver is changed).
Lee et al. does not expressly disclose where the first communication circuit which receives first data at a first data rate ; a second communication circuit which receives second data via the first communication line at a second data rate which is higher than the first data rate; determines whether the second data has an error according to a second rule which is different from the first rule
Oh et al. discloses where the first communication circuit which receives first data at a first data rate (fig.1,4A; data driver 141 receives DATA1 at first transmission speed; para.0063-0064,0076; fig.8A-para.0094); a second communication circuit which receives second data [via the first communication line] at a second data rate which is higher than the first data rate; (fig.1,4A, data driver 142 receives data DATA2 at a second transmission speed; para.0063-0064, 0076; fig.8A-para.0094).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee et al. with the teachings of Oh et al., the motivation being to provide transmission of data at different transmission speeds, thereby improving performance of the display device.
Lee et al. in view of Oh et al. do not expressly disclose the second communication circuit second data via the first communication line.
Lin et al. discloses where a first communication circuit receives data via a first communication line (fig.6, para.0029-0031; source driver SD1 receives data RSDATA including DATA1 via line L1) and a second communication circuit which receives second data via the first communication line (fig.6, para.0029-0031; source driver SD2 receives data RSDATA including DATA2 via line L1).
It would have been obvious to one of ordinary skill I the art before the effective filing date of the claimed invention to modify the device disclosed by Lee et al. in view of Oh et al., with the teachings of Lin et al., such that first and second source driver receive respective data at respective data rate (of Lee and Oh) via a first communication line (as disclosed by Lin). The motivation being to facilitate timing and skew controls, thereby preventing the source drivers from receiving data at the wrong times. In addition, the present invention enhances capacity of the RSDS interface and transmission efficiency.
Lee et al. in view of Oh et al., as modified by Lin et al., do not expressly disclose whether the second data has an error according to a second rule which is different from the first rule.
Yang et al. discloses whether the second data has an error according to a second rule which is different from the first rule (fig.3-4, para.0035,0038-0040; s318,s322,s328; if the test data signal received by the second source driver 130(2) is not in specific format, it is counted a second number of times N2, where an error rate of the second data channel 120(2) correlates to the counted second number of N2, and when the N2 is greater than a second preset threshold value (where the second preset threshold value is greater than first preset threshold value), the source driver 130(2) controls displaying of second area 150(2) of the display panel).
It would have been obvious to one of ordinary skill I the art before the effective filing date of the claimed invention to modify the device disclosed by Lee et al. in view of Oh et al., as modified by Lin et al., with the teachings of Yang et al., the motivation being so that the source drivers determine the error rates of the plurality of channels of the display according to a received test signal and preset error rates of the data channels in a way that the error rates are easily recognized.
As to Claim 4, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., disclose wherein, upon finding an error in a process of decoding the second data, the second communication circuit determines that the second data is erroneous data (Lee- fig.3-6; para.0067-0074,0105; Yang-fig.3-4).
As to Claim 5, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., disclose wherein the first communication circuit determines whether the first data has an error by checking a CRC (cyclical redundancy check) value (Lee-fig.4B-6).
As to Claim 9, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., disclose wherein the second communication circuit evaluates communication performance through a BER (Bit Error Rate) test pattern received at the second data rate (Lee-para.0046, 0061,0070, 0139,0141).
As to Claim 10, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., disclose wherein the first communication circuit receives a setting value for a BER test at the first data rate (Lee- para.0046, 0061, 0070, 0137, 0139, 0141).
As to Claim 19 is a method claim drawn to the apparatus of Claim 1 and is rejected for the reasons set forth above.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0154943) in view of Oh et al. (US 2016/0133178), further in view of Lin et al. (US 2009/0096775), and further in view of Yang et al. (US 2014/0049524), and further in view of Minagawa et al. (US 2012/0201309).
As to Claim 2, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., do not expressly disclose, but Minagawa et al. discloses: wherein the second data comprises a plurality of unit data, and the second communication circuit decodes each of the plurality unit data according to a decoding table, and, upon finding out that the unit data a unit of data included in the second data is not included in the decoding table, determines that the second data is erroneous data. (para.0033- 0034; if a code word in the bitstream is not matched to an entry in the VLC table, then an error is indicated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., such that secondary data (of Lee) is encoded with a variable length code, as disclosed by Minagawa et al, the motivation being to enable code error detection from a variable length code table and distribution of decoded data, thereby reducing processor load and time to detect an error for decoded image data.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0154943) in view of Oh et al. (US 2016/0133178), further in view of Lin et al. (US 2009/0096775), and further in view of Yang et al. (US 2014/0049524), and further in view of Gauvin et al. (US 2014/0223270).
As to Claim 3, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., do not expressly disclose, but Gauvin et al. discloses: wherein, upon finding out that the second data which is encoded by LRLC (Limited Run Length Code) has a run length that exceeds a reference value, the second communication circuit determines that the second data is erroneous data (fig.3; para.0020, 0023).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., with the teachings of Gauvin et al., the motivation being to provide classification of bit errors in run length limited data transmitted over a channel.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0154943) in view of Oh et al. (US 2016/0133178), further in view of Lin et al. (US 2009/0096775), and further in view of Yang et al. (US 2014/0049524), and further in view of Kim et al. (US 2016/0351129).
As to Claim 7, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., do not expressly disclose, but Kim et al. discloses: wherein the second communication circuit trains a communication clock at the second data rate by receiving a clock training signal, and determines whether there is a communication error by checking what clock training pattern the clock training signal has after completion of the training (fig.8, para.0075-0077,0082-0085,0100-0103).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., with the teachings of Kim et al. the motivation being so that a data driver experiencing an error may be verified using virtual feedback signal.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2015/0154943) in view of Oh et al. (US 2016/0133178), further in view of Lin et al. (US 2009/0096775), and further in view of Yang et al. (US 2014/0049524), and further in view of Alrod et al. (US 2017/0269839).
As to Claim 11, Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., do not expressly disclose, but Alrod et al. discloses: wherein the second communication circuit matches a value of M bits to a symbol consisting of N bits and includes the symbol in the second data when sending the second data, where M is a natural number and N is a natural number greater than M (fig.1, para.0012, 0015, 0028, 0034, 0036, 0062,0072,0118; received data 180 having one or more n-tuples and is mapped to m-tuple of deshaped data 182, where m<n).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Lee et al. in view of Oh et al., as modified by Lin et al. and Yang et al., with the teachings of Alrod et al., the motivation being to reduce wear to the memory and enable compensation for one or more bit errors during decoding of transformed data representations read from memory.
As to Claim 12, Lee et al. in view of Oh et al., as modified by Lin et al., Yang et, and Alrod et al. disclose wherein the second communication circuit corrects an error in a bit included in one symbol by using another symbol received before or after the one symbol (Alrod-para.0034, 0037, 0060, 0062, 0068, 0120).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2018/0114479) in view of Zhao (US 2021/0020136), further in view of Kim et al. (US 2021/0201734), and further in view of Kim et al. (US 20180122295, hereinafter Kim295).
As to Claim 13, Han et al. discloses A display driving device comprising: a first communication circuit (fig.3, timing controller 200) which sends first data and first verification data for the first data at a first data rate via a first communication line (fig.3, 13; line configuration signal and frame configuration signal via low speed driving line LNL; para.0066,0072,0100-0101,0118); and
a second communication circuit which sends second data including image data for driving pixels on a display panel via the first communication line at a second data rate which is higher than the first data rate (fig.3,13; timing controller 200; data signal via high speed driving line LNH; para.0064-0065, 0070-0073, 0075), and sends second verification data corresponding to the first verification data at the second data rate (para.0071,0075-0076,0100-0101- LD as data voltage on the basis of frame configuration signal; frame configuration signal may also be sent via high speed line).
Han et al. discloses where the timing controller (200) sends first and second data, but does not expressly disclose a second communication circuit which sends second data; first communication circuit sends first verification data, and second communication circuit sends second data via the first communication line, and sends second verification data corresponding to the first verification data.
Zhao discloses a second communication circuit which sends second data (fig.3, para.0037- timing controller includes high-speed interface 131 {read as second communication circuit} and transmits display data via the high-speed interface 131 and a low-speed interface 132 {read as first communication circuit} and transmits timing control verification signal via the low-speed interface 132); and wherein the first communication circuit sends first verification data (fig.3, para.0037-speed interface 132 {read as first communication circuit} and transmits timing control verification signal via the low-speed interface 132).
The combination of Han et al. in view of Zhao each element would have performed the same function as it did separately. Therefore, one of ordinary skill in the art would have recognized that the results of the combination would yield predictable results, in particular a first communication circuit for transmitting first data at a first data rate and second communication circuit transmitting second data at a second data rate as claimed.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device of Han et al. with the teachings of Zhao, the motivation being to provide different interfaces for transmission of data at low and high speed, and adding a verification mechanism capable of minimizing the amplitude of data of data signals to reduce electromagnetic interference while ensuring an accuracy of data transmission.
Han et al. in view of Zhao, do not expressly disclose second communication circuit sends second data via the first communication line.
Kim et al. discloses a timing controller that may transmit clock signal training signal via data clock signal line DCSL during a first period and transmit image data through clock signal line DCSL in a second period (para.0047).
It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device of Han et al. in view of Zhao, with the teachings of Kim et al., such that the first data (of Han) may be transmitted via a first line (as disclosed by Kim- line DCSL of Kim) during a first period and second data (of Han) may be transmitted via the first line (as disclosed by Kim-line DSCL of Kim). The motivation being so that the number of signal channels for signal transmission between timing controller and data driver may be reduced.
Han et al. in view of Zhao, as modified by Kim et al. do not expressly disclose second communication circuit sends second verification data corresponding to the first verification data.
In the the combination of Han in view of Zhao, as modified by Kim et al., Zhao discloses transmitting a first timing control verification signal, and when timing control verification signal and a data source verification signal are not equal to each other, the timing controller adjusts the amplitude of the data signal and proceeds to step b, in which timing control verification signal based on the adjusted data signal is generated {read as a second verification data corresponding to first verification}.
Kim295 discloses a timing controller that sends second verification data corresponding to the first verification (fig.3, para.0096-0098 timing controller adjusts the image data DATA1a based on feedback data FDa and provides the adjusted image data to the data driver {adjusted DATA1a is read as second verification data}; para.0135-0136).
It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device of Han in view of Zhao, as modified by Kim et al., with the teachings of Kim295, such that the timing controller via second communication circuit (of Zhao), sends adjusted image (as disclosed by Kim295). The motivation being to compensate for errors in the image data based on feedback data, thereby improving image quality of the display device.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2018/0114479) in view of Zhao (US 2021/0020136), further in view of Kim et al. (US 2021/0201734), further in view of Kim et al. (US 20180122295, hereinafter Kim295), and further in view of Kim et al. (US 2019/0103070, hereinafter Kim070).
As to Claim 16, Han in view of Zhao, as modified by Kim et al. and Kim295, do not expressly disclose but Kim070 discloses: wherein the second communication circuit encodes the second data by an LRLC (Limited Run Length Coding) method according to a predetermined encoding table (fig.4, 6; para.0075-0076,0090-0094).
It would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to modify the device disclosed by Han in view of Zhao, as modified by Kim et al. and Kim295, with teachings of Kim070, the motivation being prevent data of a packet from being affected by a jitter in a transmission process of the packet, so that it is possible to implement a high speed interface between a data transmission apparatus and a data reception apparatus.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2018/0114479) in view of Zhao (US 2021/0020136), further in view of Kim et al. (US 2021/0201734), further in view of Kim et al. (US 20180122295, hereinafter Kim295), and further in view of Lee et al. (US 20150154943).
As to Claim 17, Han in view of Zhao, as modified by Kim et al. and Kim295, do not expressly disclose, but Lee et al. discloses: wherein the first communication circuit sends a setting value for a BER (Bit Error Rate) test at the first data rate, and the second communication circuit sends a BER test pattern at the second data rate (fig.21, BERT mode (read as setting value) a test pattern is generated sent to timing controller embedded S-IC; para.0139,0141-0143).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Han in view of Zhao, as modified by Kim et al. and Kim295, with the teachings of Lee et al., such that configuration data sent via low speed line may include a BERT mode request and the data sent via the high speed line may include the test pattern. The motivation being to further determine whether an error exists in the signal transmission line.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (US 2018/0114479) in view of Zhao (US 2021/0020136), further in view of Kim et al. (US 2021/0201734), and further in view of Kim et al. (US 20180122295, hereinafter Kim295), and further in view of Alrod et al. (US 2017/0269839).
As to Claim 18, Han in view of Zhao, as modified by Kim et al. and Kim295, do not expressly disclose, but Alrod et al. discloses: wherein the second communication circuit matches a value of M bits to a symbol consisting of N bits and includes the symbol in the second data when sending the second data, where M is a natural number and N is a natural number greater than M (fig.1, para.0014,0023,0026-0027,0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Han in view of Zhao, as modified by Kim et al. and Kim295, with the teachings of Alrod et al., the motivation being to reduce wear to the memory and enable compensation for one or more bit errors during decoding of transformed data representations read from memory.
Allowable Subject Matter
Claim 6, 8, 14-15, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,13,19 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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