DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 01/08/2026, with respect to the rejection of previously presented dependent claim 3 (currently incorporated in claim 1) under Kim et al. (US Pub. 2022/0068194 A1) in view of Lim et al. (US Pub. 2023/0081076 A1) and further in view of Nambi et al. (US Pub. 2018/0350313 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection of claim 1 is made under Kim et al. (US Pub. 2022/0068194 A1) in view of Lim et al. (US Pub. 2023/0081076 A1) and further in view of Raghavulu et al. (US Pub. 2025/0284331 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 5-6, 9-12, 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2022/0068194 A1, hereinafter referred to as “Kim’194”) in view of Lim et al. (US Pub. 2023/0081076 A1) and Raghavulu et al. (US Pub. 2025/0284331 A1).
Regarding claim 1; Kim’194 teaches a display driving device (a display device 100, Fig.1) comprising:
[AltContent: arrow][AltContent: textbox (Main communication link)]
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(Fig.1 of Kim’194 reproduced)
a main communication circuit (a data driver 120, Fig.1) configured to receive image data (image data ODAT) and first control data (control signal DCTRL) in an active period (an active period, e.g., AP1, AP2, and AP3; Figs. 3 and 13. For example, Figs. 3 and 13, a controller 150 transmits output image data ODAT (e.g., frame data FDAT) to the data driver 120 in the active period AP1. Para. [0014], the controller may include a first scan control signal generator configured to provide a first scan control signal to the scan driver in the active period) through a main communication line (Fig.1) and to receive second control data in a blank period (para. [0014 and 0075], the controller includes a third scan control signal generator configured to generate a blank scan control signal in a variable blank period).
[AltContent: textbox (AP1)][AltContent: arrow][AltContent: connector]
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(Fig.13 of Kim’194 reproduced)
Kim’194 does not teach a driving circuit configured to drive pixels of a display panel according to the image data and to determine a power saving operation of an output circuit for driving the pixels according to a power saving control value included in the second control data.
Lim teaches a driving circuit (Fig.1, a data driver 150) configured to drive pixels of a display panel according to the image data (para. [0053]) and to determine a power saving operation of an output circuit for driving the pixels according to a power saving control value included in the second control data (Fig.4, para. [0064], a controller 170 transfers a frame configuration data FCD to the data driver 150 during a blanking period. The frame configuration data FCD includes a shut down mode bit SDMB representing whether the data driver 150 operates in a shut down mode. For example, the shut down mode bit SDMB may have a low level indicating that the data driver 150 operates in the shut down mode and a high level indicating that the data driver 150 operates in a normal driving mode. The shut down mode (e.g., Fig.8B) would be a power saving mode when a portion of components of the data driver is turned off).
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(Fig.4 of Lim reproduced)
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kim’194 to include the teaching of Lim of providing a frame configuration data FCD including a shut down mode bit during a blanking period; and driving the display device in a shut down mode or a normal driving mode based on the shut down mode bit. The motivation would have been in order to reduce power consumption (Lim, para. [0029]).
Kim’194 in view of Lim does not teach a subsidiary communication circuit configured to transmit a subsidiary communication signal through a subsidiary communication line and to indicate that the main communication circuit has entered a power saving mode through the subsidiary communication signal.
Raghavulu teaches a subsidiary communication circuit (Fig.2, a display SOC 126) configured to transmit a subsidiary communication signal (Fig.2, para.[0151], the display SOC 126 is configured to transmit a HPD signal 140 to a main SoC 108) through a subsidiary communication line (Fig.2, a HPD signal line for transmitting the HPD signal 140) and to indicate that the main communication circuit has entered a power saving mode through the subsidiary communication signal (para. [0151], the display SoC 126 transmits a HPD signal 140 to be indicative of a display panel 204 not being powered and/or otherwise operating in a power-saving mode).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim’194 in view of Lim to include the teaching of Raghavulu of configuring a display SoC to transmit a signal to a main SoC to indicate that a display panel is in a power-saving mode. The motivation would have been in order to provide a feedback signal to the timing controller.
Regarding claim 2; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 1 as discussed above. Kim’194 does not teach a power saving operation of the main communication circuit is controlled according to the power saving control value.
Lim teaches a power saving operation of the main communication circuit is controlled according to the power saving control value (Fig.4, para. 0064], the shut down mode is controlled according to the shut down mode bit in the frame configuration data FCD).
The motivation is the same as the rejection of claim 1.
Regarding claim 5; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 2 as discussed above. Kim’194 does not teach the power saving control value includes a first power saving control value for controlling the power saving operation of the main communication circuit and a second power saving control value for controlling a procedure for switching from a power saving mode to a normal mode.
Lim teaches the power saving control value includes a first power saving control value for controlling the power saving operation of the main communication circuit and a second power saving control value for controlling a procedure for switching from a power saving mode to a normal mode (see the analysis of claim 1, para. [0064], the shut down mode bit SDMB may have a low level indicating that the data driver 150 operates in the shut down mode and a high level indicating that the data driver 150 operates in a normal driving mode).
The motivation is the same as the rejection of claim 1 above.
Regarding claim 6; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 5 as discussed above. Kim’194 does not teach the main communication circuit receives a clock training signal to train a communication clock signal for receiving the image data when the second power saving control value is a first value.
Lim teaches the main communication circuit receives a clock training signal to train a communication clock signal for receiving the image data when the second power saving control value is a first value (para. [0065], the RX block 160 of the data driver 150 may include a clock data recovery (CDR) circuit that recovers a clock signal and data, and the CDR circuit may perform a clock training operation that adjusts or corrects a frequency and/or a phase of the recovered clock signal based on the clock training pattern CTP).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kim’194 to include the teaching of Lim of providing a clock training pattern to train the clock signal. The motivation would have been in order to correct a frequency and/or a phase of the clock signal (Lim, para. [0065]).
Regarding claim 9; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 1 as discussed above. Kim’194 does not teach the main communication circuit receives symbols composed of N (N being a natural number equal to or greater than 2) bits and matches each symbol with the power saving control value composed of M (a natural number less than N) bits.
Lim teaches the main communication circuit receives symbols composed of N (N being a natural number equal to or greater than 2) bits and matches each symbol with the power saving control value composed of M (a natural number less than N) bits (para. [0101], the frame configuration data comprises only a shut down mode bit, but also at least one set of same data region start bits SB1 and SB2, and same data region end bits EB1 and EB2 representing at least one same data region SDR1 and SDR2. It is understood that each bit of the frame configuration data would be compared to match with one bit of shut down mode bit, same data region start bits, and same data region end bits so as to determine whether the data driver will be operating in a shut down mode or a normal mode, and determine a shut down region).
The motivation is the same as the rejection of claim 1.
Regarding claim 10; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 1 as discussed above. Kim’194 does not explicitly teach the driving circuit comprises a latch circuit configured to latch the image data per pixel, a digital-to-analog converter (DAC) configured to convert output data of the latch circuit into an analog data voltage, and an output buffer configured to output the data voltage to a pixel, wherein on/off of the DAC and the output buffer is determined according to the power saving control value.
Lim teaches the driving circuit (a data driver 150a, Fig.7) comprises a latch circuit (a latch block 220, Fig.7) configured to latch the image data per pixel (para. [0069 and 0078]), a digital-to-analog converter (DAC) (a DAC block 270, Fig.7) configured to convert output data of the latch circuit into an analog data voltage (Fig.7, para. [0069]), and an output buffer (an output buffer OB block 280, Fig.7) configured to output the data voltage to a pixel (para. [0069]), wherein on/off of the DAC and the output buffer is determined according to the power saving control value (Fig.8B, para. [0084], in the shut down mode, some output buffers are turned off).
The motivation is the same as the rejection of claim 1.
Regarding claim 11; Kim’194 teaches a display driving device comprising: a processing circuit configured to process image data for driving pixels of a display panel (Kim’194, para. [0056], a controller 150 receives input image data IDAT from a host processor); and a main communication circuit configured to transmit the image data and first control data in an active period through a main communication line (For example, Figs. 3 and 13 of Kim’194, a controller 150 transmits output image data ODAT (e.g., frame data FDAT) to the data driver 120 in the active period AP1. Para. [0014], the controller may include a first scan control signal generator configured to provide a first scan control signal to the scan driver in the active period). Kim’194 does not teach a main communication circuit configured to transmit second control data including a power saving control value in a blank period).
Kim’194 does not teach that the main communication circuit configured to transmit second control data including a power saving control value in a blank period; and wherein the main communication circuit transmits a value indicating a normal operation of a driving device through the power saving control value, and transmits a clock training signal to the driving device.
Lim teach a main communication circuit configured to transmit second control data including a power saving control value in a blank period (Fig.4, para. [0064], a controller 170 transfers a frame configuration data FCD to the data driver 150 during a blanking period. The frame configuration data FCD includes a shut down mode bit SDMB representing whether the data driver 150 operates in a shut down mode. For example, the shut down mode bit SDMB may have a low level indicating that the data driver 150 operates in the shut down mode and a high level indicating that the data driver 150 operates in a normal driving mode. The shut down mode (e.g., Fig.8B) would be a power saving mode when a portion of components of the data driver is turned off); and wherein the main communication circuit transmits a value indicating a normal operation of a driving device through the power saving control value, and transmits a clock training signal to the driving device (para. [0064], the shut down mode bit SDMB includes a second value (e.g., low level) indicating that the data driver operates in a normal driving mode. Para. [0065], the controller may transfer a clock training pattern CTP as the output image data ODAT to the data driver 150 through the data transfer line DTL).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kim’194 to include the teaching of Lim of providing a frame configuration data FCD including a shut down mode bit during a blanking period; and driving the display device in a shut down mode or a normal driving mode based on the shut down mode bit. The motivation would have been in order to reduce power consumption (Lim, para. [0029]).
Kim’194 in view of Lim does not teach a subsidiary communication circuit configured to receive a subsidiary communication signal through a subsidiary communication line.
Raghavulu teaches a subsidiary communication circuit configured to receive a subsidiary communication signal through a subsidiary communication line.
Raghavulu teaches a subsidiary communication circuit (a main SoC 108, Fig.2) configured to receive a subsidiary communication signal through a subsidiary communication line (para. [0151], the display SoC 126 transmits a HPD signal 140 to the main SoC 108 to be indicative of a display panel 204 not being powered and/or otherwise operating in a power-saving mode).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim’194 in view of Lim to include the teaching of Raghavulu of configuring a display SoC to transmit a signal to a main SoC to indicate that a display panel is in a power-saving mode. The motivation would have been in order to provide a feedback to the controller.
Regarding claim 12; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 11 as discussed above. Kim’194 does not teach a subsidiary communication circuit configured to receive a subsidiary communication signal through a subsidiary communication line, wherein the main communication circuit transmits a value indicating a power saving operation of one driving device through the power saving control value, and the subsidiary communication circuit confirms that the driving device has entered a power saving mode through the subsidiary communication signal.
Lim teaches a subsidiary communication circuit (a receiving RX block 160, Fig.1) configured to receive a subsidiary communication signal (the frame configuration data FCD, Fig.4) through a main communication line (a data transfer line DTL, Fig.1), wherein the main communication circuit transmits a value indicating a power saving operation of one driving device through the power saving control value (para. [0064], the frame configuration data FCD includes a shut down mode bit SDMB representing whether the data driver 150 operates in a shut down mode. For example, the shut down mode bit SDMB may have a low level indicating that the data driver 150 operates in the shut down mode).
The motivation is the same as the rejection of claim 11 above.
Raghavulu teaches a subsidiary communication circuit configured to receive a subsidiary communication signal through a subsidiary communication line, and the subsidiary communication circuit confirms that the driving device has entered a power saving mode through the subsidiary communication signal (see the analysis of claim 11 above).
The motivation is the same as the rejection of claim 11.
Regarding claim 16; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 11 as discussed above. Kim’194 does not teach the power saving control value includes a first power saving control value for controlling a power saving operation of one driving device and a second power saving control value for controlling a procedure for switching from a power saving mode to a normal mode.
Lim teaches the power saving control value includes a first power saving control value for controlling a power saving operation of one driving device and a second power saving control value for controlling a procedure for switching from a power saving mode to a normal mode (see the analysis of claim 1, for example, para. [0064], the controller 170 transfers a frame configuration data FCD to the data driver 150 during a blanking period. The frame configuration data FCD includes a shut down mode bit SDMB representing whether the data driver 150 operates in a shut down mode. For example, the shut down mode bit SDMB may have a low level indicating that the data driver 150 operates in the shut down mode and a high level indicating that the data driver 150 operates in a normal driving mode).
The motivation is the same as the rejection of claim 11.
Regarding claim 17; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 11 as discussed above. Kim’194 does not teach the main communication circuit sets the second power saving control value to a first value and transmits a clock training signal to the driving device after a predetermined time has elapsed.
Lim teaches the main communication circuit sets the second power saving control value to a first value and transmits a clock training signal to the driving device after a predetermined time has elapsed (Fig.4, the ODAT includes the frame configuration data FCD and a clock training pattern CTP. The frame configuration data includes a shut down mode bit. The clock training pattern is transmitted after the FCD a predetermined time).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kim’194 to include the teaching of Lim of providing a clock training pattern to train the clock signal. The motivation would have been in order to correct a frequency and/or a phase of the clock signal (Lim, para. [0065]).
Regarding claim 19; Kim’194 in view of Lim and Raghavulu teaches a display driving method comprising; receiving image data and first control data in an active period through a main communication line; receiving second control data in a blank period; and driving pixels of a display panel according to the image data and determining a power saving operation of an output circuit according to a power saving control value included in the second control data; controlling a power saving operation of a main communication circuit according to the power saving control value: and transmitting a subsidiary communication signal through a subsidiary communication line and indicating that the main communication circuit has entered a power saving mode through the subsidiary communication signal (similar to the analysis of claim 1).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2022/0068194 A1, hereinafter referred to as “Kim’194”) in view of Lim et al. (US Pub. 2023/0081076 A1) and Raghavulu et al. (US Pub. 2025/0284331 A1) as applied to claim 1 above; further in view of Matsuda et al. (US Pub. 2016/0232874 A1).
Regarding claim 4; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 1 as discussed above. Kim’194 does not teach the main communication circuit receives a clock training signal to train a communication clock signal for receiving the image data, and the subsidiary communication signal indicates that the main communication circuit has entered a normal mode after training of the communication clock signal through the subsidiary communication signal.
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(Fig.2 of Matsuda reproduced)
Matsuda teaches the main communication circuit receives a clock training signal (training data, Fig.2) to train a communication clock signal for receiving the image data (para. [0035], in a second mode, a first transmission unit 11 of a transmission device 10 transmits training data to a first reception unit 21 of a reception device 20), and the subsidiary communication signal (a mode switching notification signal transmitted through a second signal line 50, Fig.2) indicates that the main communication circuit has entered a normal mode after training of the communication clock signal through the subsidiary communication signal (Fig.3, para. [0031-0040], the display device may be operating in a first mode (i.e., a normal mode) and a second mode (i.e., a training mode). After the display device operates in a second mode (i.e., training), the mode switching notification signal indicates that the display device enters a first mode).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display system of Kim’194 in view of Lim and Raghavulu to include the teaching of Matsuda of generating a mode switching notification signal indicating that the display device enters a first (normal) mode after a clock training period. The motivation would have been in order to suppress a lack of image data reception by a reception device (Matsuda, para. [0010 and 0014]).
Claim 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2022/0068194 A1, referred to as “Kim’194”) in view of Lim et al. (US Pub. 2023/0081076 A1) and Raghavulu et al. (US Pub. 2025/0284331 A1) as applied to claim 12 above, and further in view of Ahn et al. (US Pub. 2020/0035144).
Regarding claim 13; Kim’194 in view of Lim and Raghavulu teaches the display driving device of claim 12 as discussed above. Kim’194 does not teach the main communication circuit operates in the power saving mode for a predetermined time upon confirming that the driving device has entered the power saving mode.
Ahn teaches the main communication circuit operates in a safe mode for a predetermined time upon confirming that the driving device has entered the safe mode (Fig.4, para. [0082], a display driving circuit comprises a timing controller configured to receive state information ST1-ST4 from a source driving circuits (141-144). In particular, when the state information signal ST1 maintains the low level for more than a predetermined period of time, the receiver 125 of the timing controller 120 determines that the source driving circuit 141 is in the abnormal state and outputs the mode signal MD indicating the safe mode).
At the time of invention was effectively filed, it would have been obvious to one of ordinary skill in the art to modify the display device of Kim’194, Lim, and Raghavulu to include the teaching of Ahn of determining a display device to be operating in a safe mode after a predetermined period. Accordingly, a feedback signal indicative of power saving mode would be transmitted after a predetermined period when the display device is operating in the power saving mode. The motivation would have been in order to correctly generate the feedback signal.
Allowable Subject Matter
Claims 7-8, 14, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art fails to teach all limitations recited in claims 7, 14, and 18.
Inquiries
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN H TRUONG whose telephone number is (571)270-1630. The examiner can normally be reached M-F: 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached at 571-272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NGUYEN H TRUONG/Examiner, Art Unit 2623
/CHANH D NGUYEN/Supervisory Patent Examiner, Art Unit 2623