Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
Papers submitted under 35 U.S.C. 119(a)-(d) have been placed of record in the file.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 27-30 and 32-38, are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Ueda US Pub. No. 20070130425.
As per claims 27-30, 32-33 and 37, Figs. 1, 3 and 5 of Ueda are directed to memory-control logic coupled operatively to read-destructive computer memory (Fig. 1, abstract, par. 38), the memory-control logic comprising: an instruction decoder (301, Fig. 3, par. 52) configured to receive a read instruction and to determine a read address (par. 52) in the computer memory corresponding to the read instruction, the read address referencing a cell (S401, Fig. 4) within a row of the computer memory; writeback logic (302, Fig. 3, par. 48) configured to determine a discard state for data stored in the row (S403, Fig. 4) according to a usage of the data, the discard state being positive for data to be read only once (S505, Fig. 5, par. 6, 7 or 10) and negative for data to be read more than once (S502, Fig. 5); a row reader (301, Fig. 3 and par. 52 or 53) configured to read the data from the row; and a row writer (302, Fig. 2, par. 60) configured to write the data back to the row if the discard state is negative (pars. 48, 59 and 60, S502), and to return without writing the data back to the row if the discard state is positive (par. 6, 61 and 62, S504).
As per claims 34-36, Fig. 5 of Ueda discloses further comprising, prior to receiving the read instruction (S502): receiving a write instruction (S501), wherein the discard state is forecasted based at least in part on the write instruction; writing the data (S503) to the computer memory.
As per claim 38, a paragraph 5 of Ueda discloses wherein the computer memory comprises dynamic random-access memory (DRAM).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claims 20-26, 31 and 39 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Ueda US Pub. No. 20070130425 in view of Kim et al. US Pub. No. 20200160157.
As per claim 31, Fig. 3 of Ueda discloses wherein reading and writing the data but fails to disclose asserting one or more strobe lines of the memory-control logic, and wherein the one or more strobe lines are asserted differently depending on the discard state. However, a paragraph 62 of Kim discloses one or more strobe lines (row column address strobes) of the memory-control logic (200, Fig. 2). It would have been obvious to a person of ordinary skill in the art at the time invention was made to recognize that Ueda would have the strobes as taught by Kim in order to latch the row and column addresses to access the memory device.
As per claim 39, Ueda fails to disclose wherein the computer memory is arranged in a neural-processing unit (NPU). However, Fig. 2 of Kim discloses a neural-processing unit (NPU) (400). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Ueda’s memory device including a neural network system as taught by Kim in order to provide a method and apparatus for reducing the time required for data transmission and increasing the power efficiency of a system in a memory device and a neural network system including the memory device (par. 5).
As per claims 20-21, and 24-26, claims 20-21, and 24-26 are rejected the same rejections of claims 27, 31-33, 37 and 39 above. It is noted that the independent claim 20 is identical to the independent claims 27 and 37 except a limitation “neural-network processing” in the claim 20. However, this limitation is disclosed by a block 400 in Fig. 2 of Kim as rejected in the claim 39.
As per claim 22, Ueda fails to discloses the limitations in claim 22. However, a paragraph 44 and Fig. 3 of Kim disclose these limitations of claim 3 wherein the discard state is negative when the layer is an output layer (Ln) and positive when the layer is an input layer (L1) or an intermediate layer (L2). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Ueda’s computer which utilizes the neutral network including different layers as taught by Kim in order to perform other types of operations (par. 44).
As per claim 23, Ueda fails to discloses the limitations in claim 23. However, a paragraph 46 and Fig. 3 or 4A of Kim disclose these limitations of claim 23 wherein the discard state is negative when the data corresponds to a weighting coefficient (W) of the neural network. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Ueda’s computer which utilizes the weighting coefficient as taught by Kim in order to provide the weight values as an input feature map (par. 46).
8. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827