DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-7 are pending and have been examined.
Specification
The abstract of the disclosure is objected to because it is undue length by exceeding 150 words . A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3-7 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 requires “forming a P-shaped field limiting ring.” This is not described.
Page 1, second column, paragraph 2, sentence 11, of the specification, states “forming a P-shaped field limiting ring” but lacks description of a P-shaped ring.
Claims 4-7 depend on claim 3 and are unsupported due to their dependence on unsupported claim 3.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over (Fang et al. (US 20220045207 A1 – hereinafter Fang) in view of Neilson (US 4158206 A) and Ebiike et al. (US 20190348524 A1 – hereinafter Ebiike).
Regarding independent claim 1, Fang teaches:
A split-gate silicon carbide device ([0009] – “a split-gate structure
provided with a trench passing through the well region and the body region and extending to the substrate”) with a buried field limiting ring, characterized in that comprises, from bottom to top, a drain electrode, a drift region and a P-well region, and further comprises:
a trench, which runs through the P-well region;
a P-type field limiting ring, which is formed on the periphery of the trench bottom;
a P+ region and an N+ region, which are connected each other and formed on the P-well region on both sides of the trench;
a gate electrode ([0054] – “a gate (not shown in FIG. 3)”), which is formed in the trench ([0053] – “trench” – Fig. 3 shows a trench), including a transistor gate (235 – Fig. 3 – [0062] – “polysilicon body 235 leads out the gate 280” – this corresponds to the transistor gate) located on the outer side and a field limiting ring contact plug (260 – Fig. 3 – [0053] – “conductive plug 260”) located in the middle region, the transistor gate (235) being wrapped with an oxide layer (234 – Fig. 3 – [0053] – “second oxide layer 234”), the top of the field limiting ring contact plug (260) being connected to the source electrode (250 – Fig. 3 – [0054] – “source 250”), the bottom of the field limiting ring contact plug (260) being connected to the P-type field limiting ring (232 – Fig. 3 – {[0055] – “the first polysilicon body is connected to the source, which can reduce the capacitance of the gate-drain”} – this is interpreted as reducing the electric field, {[0053 – “A first polysilicon body 232 is formed at the bottom of the trench”} – this is interpreted that 232 in a field limiting ring); and
a source electrode (250), which covers the surface of the device (Fig. 3 shows this),
wherein the P-type field limiting ring (232) is connected to the source electrode (250) by the field limiting ring contact plug (260), achieving equipotential with the source electrode to reduce the electric field ([0055] – “the first polysilicon body is connected to the source, which can reduce the capacitance of the gate-drain” – this is interpreted as reducing the electric field) in the gate oxide layer (231 and 234 – Fig. 3 – [0053] – “first oxide layer 231 … second oxide layer 234”) on both sides of the trench, so that the device depletion region is limited to the outside of the channel region ([0055] – “When a voltage is applied to the gate, an inversion layer is formed in the body regions at two sides of the trench through the second polysilicon body and the second oxide layer, thereby forming a conductive channel to make the source-drain turned on”) on both sides of the trench in the reverse bias state ([0055] – “When a voltage is applied to the gate” – this is interpreted as the reverse bias state).
Fang does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Neilson teaches
a buried field limiting ring (24 – Fig. 1 – [3:64 – 4:6] – “because the point of minimum distance between the rings 24 is within the body 12 rather than at the surface 14 the field limiting rings 24” – these are within the body below the surface thus buried).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the field limiting ring structure as taught by Neilson into Fang.
An ordinary artisan would have been motivated to use the known technique of Neilson in the manner set forth above to produce the predictable results of [1:24-35] – “Conventional field limiting rings, however, are themselves surface limited to the degree that excess charges are always present at the surface intercepts thereof. Hence, while the reverse bias breakdown voltage of the PN junction is improved it nevertheless remains surface limited. The usual solution to the problem of surface charge is to provide better surface passivation to reduce the number of mobile charges thereat. One such solution is described in U.S. Pat. No. 3,971,061 issued to Matsushita et al. on July 20, 1976, wherein a layer of high-resistivity polycrystalline silicon material is used as a passivant over the field limiting rings.”
Fang and Neilson does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ebiike teaches
characterized in that comprises, from bottom to top, a drain electrode (25 – Fig. 1 – [0035] – “drain electrode 25”), a drift region (12 – Fig. 1 – [0035] – “drift layer 12”) and a P-well region (13 – Fig. 1 – [0036] – “well region 13 has a p-type”), and further comprises:
a trench (31 – Fig. 1 – [0037] – “trench 31”), which runs through the P-well region (13 – Fig. 1 shows this);
a P-type field limiting ring (16 – Fig. 1 – [0035] – “electric field relaxation region 16”), which is formed on the periphery of the trench bottom (31 – Fig. 1 – [0037] – “trench 31”);
a P+ region (15 – Fig. 1 – [0036] – “well contact region 15 has the p-type”) and an N+ region (14 – Fig. 1 – [0036] – “source region 14 has the n-type”), which are connected each other and formed on the P-well region (13 – Fig. 1 – [0036] – “well region 13 has a p-type”) on both sides of the trench (31 – Fig. 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Ebiike into Fang and Neilson.
An ordinary artisan would have been motivated to use the known technique of Ebiike in the manner set forth above to produce the predictable results of resolving the issues described in [0002] – [0006].
Regarding claim 2, Fang as modified by Neilson and Ebiike, teaches claim 1 from which claim 2 depends. Fang and Neilson does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ebiike teaches
characterized in that,
the depth of the transistor gate (22 is the gate electrode therefor the structure is the transistor gate as shown in Fig. 3) is greater than the depth of the P-well region (13 – Fig. 2 – [0036] – “well region 13 has a p-type”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Ebiike into Fang and Neilson.
An ordinary artisan would have been motivated to use the known technique of Ebiike in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding independent claim 3, Fang teaches:
A method of preparing a split-gate silicon carbide device ([0009] – “a
split-gate structure provided with a trench passing through the well region and the body region and extending to the substrate”) with a buried field limiting ring, characterized in that,
comprises the following steps:
forming a P-well region on the upper part of an N-doped SiC substrate, forming an N+ drain at the bottom, and using the other region as a drift region;
forming a P+ region and an N+ region being adjacent to the P+ region on both sides of the upper part of the P-well region;
forming a trench that runs through the P-well region with the bottom of the trench being located in the drift region and the sidewall of the trench being adjacent to the N+ region on both sides;
forming a P-shaped field limiting ring by self-aligning on the periphery of the trench bottom;
forming, in the trench ([0053] – “trench” – Fig. 3 shows a trench), a transistor gate (235 – Fig. 3 – [0062] – “polysilicon body 235 leads out the gate 280” – this corresponds to the transistor gate) wrapped with an oxide layer (234 – Fig. 3 – [0053] – “second oxide layer 234”) on the outer side and a field limiting ring contact plug (260 – Fig. 3 – [0053] – “conductive plug 260”) in the middle region, and the bottom of the field limiting ring contact plug (260) being connected with the P-type field limiting ring (232 – Fig. 3 – {[0055] – “the first polysilicon body is connected to the source, which can reduce the capacitance of the gate-drain”} – this is interpreted as reducing the electric field, {[0053 – “A first polysilicon body 232 is formed at the bottom of the trench”} – this is interpreted that 232 in a field limiting ring);
forming a source electrode (250 – Fig. 3 – [0054] – “source 250”) on the surface of the device, connecting the source electrode (250) to the top of the field limiting ring contact plug (260);
wherein, the P-type field limiting ring (232) is connected with the source electrode (250) by the field limiting ring contact plug (260), achieving equipotential with the source electrode (250) to reduce the electric field ([0055] – “the first polysilicon body is connected to the source, which can reduce the capacitance of the gate-drain” – this is interpreted as reducing the electric field) in the gate oxide layer (231 and 234 – Fig. 3 – [0053] – “first oxide layer 231 … second oxide layer 234”) on both sides of the trench, so that the device depletion region is limited to the outside of the channel region ([0055] – “When a voltage is applied to the gate, an inversion layer is formed in the body regions at two sides of the trench through the second polysilicon body and the second oxide layer, thereby forming a conductive channel to make the source-drain turned on”) on both sides of the trench in the reverse bias state ([0055] – “When a voltage is applied to the gate” – this is interpreted as the reverse bias state).
Fang does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Neilson teaches
a buried field limiting ring (24 – Fig. 1 – [3:64 – 4:6] – “because the point of minimum distance between the rings 24 is within the body 12 rather than at the surface 14 the field limiting rings 24” – these are within the body below the surface thus buried).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the field limiting ring structure as taught by Neilson into Fang.
An ordinary artisan would have been motivated to use the known technique of Neilson in the manner set forth above to produce the predictable results as stated above in claim 1.
Fang and Neilson does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Ebiike teaches
comprises the following steps:
forming a P-well region (13 – Fig. 1 – [0036] – “well region 13 has a p-type”) on the upper part of an N-doped SiC substrate (11 – Fig. 1 – [0036] – “the SiC substrate 11 has the same conductivity type as the drift layer 12. The drift layer 12 has an n-type (first conductivity type)”), forming an N+ drain (25 – Fig. 1 – [0040] – “drain electrode 25 preferably forms ohmic contact with the SiC substrate 10 11” – since this is an ohmic contact with the substrate, it must be a more positive charge than the negative substrate thus it is interpreted as a N+ drain) at the bottom ( Fig. 1 shows this), and using the other region as a drift region (12 – Fig. 1 – [0036] – “drift layer 12 has an n-type (first conductivity type)”);
forming a P+ region (15 – Fig. 1 – [0036] – “well contact region 15 has the p-type”) and an N+ region (14 – Fig. 1 – [0036] – “source region 14 has the n-type”) being adjacent to the P+ region (15) on both sides of the upper part of the P-well region (13 – Fig. 1 shows this);
forming a trench (31 – Fig. 1 – [0037] – “trench 31”) that runs through the P-well region (13) with the bottom of the trench being located in the drift region (12) and the sidewall of the trench being adjacent to the N+ region (14) on both sides (Fig. 1 shows this);
forming a P-shaped field limiting ring (16 – Fig. 1 – [0035] – “electric field relaxation region 16”) by self-aligning on the periphery of the trench bottom (Fig. 1 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Ebiike into Fang and Neilson.
An ordinary artisan would have been motivated to use the known technique of Ebiike in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 4, Fang as modified by Neilson and Ebiike, teaches claim 3 from which claim 4 depends. Fang further teaches
isolating the transistor gate (235) by the self-aligned oxide layer
sidewall (234 – Fig. 3 – [0053] – “second oxide layer 234”), and at the same time, obtaining a filling region of the field limiting ring contact plug (260).
Fang and Neilson does not expressly disclose the other limitations of claim 4.
However, in an analogous art, Ebiike teaches
characterized in,
self-aligning to form a split-gate structure by etching the gate material ([0050] – “the gate trench 31 is formed using lithography technique and etching technique. The p-type electric field relaxation region 16 and the n-type surge relaxation region 17 are formed at the bottom of the gate trench 31 using ion implantation technique, for example”),
isolating the transistor gate by the self-aligned oxide layer sidewall, and at the same time, obtaining a filling region of the field limiting ring contact plug.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the gate structure as taught by Ebiike into Fang and Neilson.
An ordinary artisan would have been motivated to use the known technique of Ebiike in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 5, Fang as modified by Neilson and Ebiike, teaches claim 4 from which claim 5 depends. Fang further teaches
characterized in that,
the steps of forming a transistor gate (235) wrapped with an oxide layer
(234) include: forming an oxide layer at the bottom (231 and 234 – Fig. 3 – [0053] – “first oxide layer 231 … second oxide layer 234”) and sidewall (234) of the trench;
depositing a polycrystalline silicon layer (235 – Fig. 3 – [0062] – “polysilicon
body 235 leads out the gate 280” – this corresponds to the transistor gate) to cover the oxide layer (231 and 234) and completely fill the trench;
depositing an oxide layer to cover the surface of the device, defining a metal filling region by means of photolithography, etching the oxide layer and the polycrystalline silicon layer to expose the P+ region surface and part of the N+ region surface on both sides of the trench, and exposing the surface of the oxide layer in the middle region at the bottom of the trench, thereby separating the polycrystalline silicon layer to form a split-gate structure serving as a transistor gate;
depositing the oxide layer and etching it back, forming an isolation sidewall on the sidewall of the transistor gate, thereby wrapping the transistor gate with the oxide layer (S200 – Fig. 9 – this describes this process).
Fang and Neilson does not expressly disclose the other limitations of claim 4.
However, in an analogous art, Ebiike teaches
depositing an oxide layer to cover the surface of the device, defining a metal filling region by means of photolithography, etching the oxide layer and the polycrystalline silicon layer to expose the P+ region surface and part of the N+ region surface on both sides of the trench, and exposing the surface of the oxide layer in the middle region at the bottom of the trench, thereby separating the polycrystalline silicon layer to form a split-gate structure serving as a transistor gate ([0049] – “the p-type well region 13, the n-type source region 14, and the p-type well contact region 15 are formed using publicly-known lithography technique and ion implantation technique, etc. Each of these region is formed by ion implantation performed by using a mask that can be a resist or an oxide film processed by photolithography, for example. Ions to be used are aluminum (Al) ions for formation of the p-type region, and nitrogen (N) ions for formation of the n-type region, for example”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the formation method as taught by Ebiike into Fang and Neilson.
An ordinary artisan would have been motivated to use the known technique of Ebiike in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 6, Fang as modified by Neilson and Ebiike, teaches claim 5 from which claim 6 depends. Fang further teaches
characterized in that,
the steps of forming the field limiting ring contact plug (260) and the source electrode (250) include:
etching the oxide layer, exposing the P-type field limiting ring in the middle region at the bottom of the trench;
forming a metal to completely fill the trench and cover the device surface, using the metal layer filled in the trench as a field limiting ring contact plug, and using the metal layer covering the device surface as a source electrode (Claim 13 – “A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate, and the substrate having a first conductivity type; forming a split-gate structure on the substrate, comprising: providing a trench on the substrate; forming a first oxide layer on a side wall of the trench; forming a first polysilicon body at a bottom of the trench; etching off the first oxide layer located above the first polysilicon body; forming an isolation structure on the first polysilicon body and the first oxide layer; forming a second oxide layer on a side wall of the trench located above the isolation structure; forming a second polysilicon body on the second oxide layer and the isolation structure, the second polysilicon body not full filling the trench; and etching the second polysilicon body to remove the second polysilicon body at the bottom of the trench and retain the second polysilicon body on the side wall of the trench; doping an upper surface layer of the substrate to form a body region in contact with the second oxide layer, and the body region having a second conductivity type; doping the body region to form a well region in contact with the second oxide layer, the well region having a first conductivity type; forming an interlayer dielectric layer on a surface of the well region and a surface of the split-gate structure, the interlayer dielectric layer being filled into the trench; forming a conductive plug, the conductive plug passing through the interlayer dielectric layer and the isolation structure in the trench, and extending into the first polysilicon body, the conductive plug and the second polysilicon body being isolated from each other by the interlayer dielectric layer; and leading out a source, a gate, and a drain, the source passing through the well region and extending to the body region, the source being connected to the conductive plug, the gate passing through the interlayer dielectric layer and being connected to the second polysilicon body, the drain being formed on a lower surface of the substrate” – describes this process).
Regarding claim 7, Fang as modified by Neilson and Ebiike, teaches claim 3 from which claim 7 depends. Fang further teaches
characterized in that,
the upper surface of the oxide layer (231) at the bottom of the trench is lower than the lower surface of the P-well region (222 – Fig. 3 – [0052] – “well region 222”).
Pertinent Art
For the benefits of the Applicant, US 20240387722 A1 and US 20220320295 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including light-emitting/receiving element, or a second light-emitting layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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