Prosecution Insights
Last updated: July 17, 2026
Application No. 18/716,190

3D-SHAPED MODULE WITH INTEGRATED DEVICES AND METHOD

Non-Final OA §103
Filed
Jun 04, 2024
Priority
Dec 06, 2021 — EU 21212559.5 +1 more
Examiner
ABRAHAM, JOSE K
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nederlandse Organisatie Voor Toegepast-natuurwetenschappelijk Onderzoek Tno
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
298 granted / 360 resolved
+14.8% vs TC avg
Strong +34% interview lift
Without
With
+34.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
40 currently pending
Career history
396
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
72.4%
+32.4% vs TC avg
§102
3.9%
-36.1% vs TC avg
§112
23.4%
-16.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 360 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 04 June 2024 was filed prior to the mailing date of this office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election of Group I, claims 1-9 and 20 in the reply filed on 20 April 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Claims 10-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Claim Objections Claims 1-2, 4-6 and 9 are objected to because of the following informalities: In claim 1, lines 2 and 5: “one or more integrated electronic device” should read: -- one or more integrated electronic devices -- In claim 1, line 7: “disposed along a backward face of” should read: -- disposed along a back face of -- In claim 1, line 11 and claim 6, line 4: “mould” should read: -- mold -- In claim 1, lines 6, 7, 9, and 12, claim 5, line 2, and claim 9, line 2: “the buffer layer” should read: -- the thermomechanical buffer layer -- In claim 1, lines 13-15: “wherein the thermomechanical buffer layer is comprised of a thermoplastic composition having a storage modulus that is within a range of 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate during the thermoforming.” should read: -- wherein during the thermoforming, the thermomechanical buffer layer comprised of a thermoplastic composition having a storage modulus in a range from 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate.” In claim 2, line 2, and claim 6, line 4: “backward face” should read: -- back face --- In claim 2, line 4: “one or more integrated electronic device” should read: -- one or more integrated electronic devices -- In claim 4, line 2 and claim 6 line 4: “has a storage modulus” should read: -- has the storage modulus --. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Torvinen (US 20180149321). Regarding claim 1, Torvinen teaches, a method of manufacturing a thermoformed structural electronics module (Figs. 1 to 6) comprising one or more integrated electronic device (integration of electronics, see Fig. 1, para. [0003-0005]), the method comprising: [AltContent: textbox (electronic device)][AltContent: ][AltContent: textbox (thermoplastic carrier substrate (polycarbonate or PMMA) )][AltContent: ][AltContent: textbox (thermomechanical buffer layer (TPU))][AltContent: arrow] PNG media_image1.png 298 471 media_image1.png Greyscale Annotated Fig. 5, Torvinen. applying a thermomechanical buffer layer (material layer 106, see annotated Fig. 5, molded material of layer 106 may incorporate…thermoplastic polyurethane, TPU, para. [0095]) along a face of a thermoplastic carrier substrate (substrate 102, Fig. 5, substrate film layer 102…comprise, at least one material selected from the group consisting of PMMA (Polymethyl methacrylate), Poly Carbonate (PC), para. [0079]); providing electronic wiring (electrode 508, the electrode 508 could be provided on the (top) face of the molded layer 106, Fig. 5, para. [0157]) and the one or more electronic device (optical element 504, Fig. 5, feature 504 refers to an optical element, electronics such as a number of light sources may be arranged on the substrate film,…various integrated circuits contemplated hereinbefore, para. [0134]) onto the buffer layer forming a stack wherein the electronic wiring and the at least one electronic device are disposed along a backward face of the buffer layer (electrode 508 may be electrically or electromagnetically coupled to control electronics that are included in the structure 500, 600, para. [0158]), opposite the carrier substrate (see Fig. 5); followed by thermoforming the stack (molding, see para. [0148-0152]), including the carrier substrate and the buffer layer with the electronic device and corresponding electronic wiring provided thereon to a thermoformed stack in a mould under application of pressure and heat (pressure applied on a target film obtained either by pressing mechanically air into the mold,…the mold temperature about 20 to 95 degrees Celsius, e.g. about 80 degrees Celsius, para. [0116-0117]) at a plasticizing condition of the carrier substrate and the buffer layer, and wherein the thermomechanical buffer layer (thermoplastic polyurethane, TPU, para. [0095]) is comprised of a thermoplastic composition having a storage modulus that is within a range of 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate (PMMA (Polymethyl methacrylate), Poly Carbonate (PC), para. [0079]) during the thermoforming (see Note below). Torvinen teaches, the thermomechanical buffer layer 106 comprising thermoplastic polyurethane formed on a thermoplastic carrier substrate 10 comprising PMMA, alternatively polycarbonate substrate. Instant application discloses in para. [0047-0049], the thermomechanical buffer layer 2 in Fig. 1A as thermoplastic polyurethane and thermoplastic carrier substrate 3 as, polycarbonate material. Therefore, in view of the teachings of Torvinen, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the thermoformed structural electronic module of Torvinen as disclosed in para. [011-0117] so that it enables forming desired properties of the electronic module by properly fixing the thermoformed structural electronic module as Torvinen disclosed in para. [0047-0049]. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in molding the electronic module, or thermoforming the stack. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success. Note 1: If the prior art product is the same or substantially the same as the claimed product, the claimed properties or functions are presumed to be inherent. See MPEP § 2112.01. Since Torvinen teaches identical composition as disclosed in claim 1, the prior art composition would have the identical storage modulus as applicant recited in the limitation and hence Torvinen meets the limitation “the thermomechanical buffer layer is comprised of a thermoplastic composition having a storage modulus that is within a range of 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate during the thermoforming”. Applying a known technique to a known method, or product, ready for improvement to yield predictable results, see MPEP § 2143. Regarding claim 2, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to claim 1, further comprising providing a backing layer (606, see annotated Fig. 6 below) of a structural support material along a backward face of the thermoformed stack opposite the carrier substrate, said backing layer encapsulating the one or more electronic device and at least part of the corresponding electronic wiring (see Fig. 6). [AltContent: textbox (backing layer)][AltContent: arrow] PNG media_image2.png 302 506 media_image2.png Greyscale Annotated Fig. 6, Torvinen. Regarding claim 3, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to claim 1, wherein the heat for thermoforming the stack is predominantly supplied from a carrier side of the stack (see para. [0108], unless otherwise defined, applying heat to the stack in a mold is of design choice). Regarding claim 4, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to claim 1, wherein the thermoplastic composition has a storage modulus that is within 0.02-2.5% of a storage modulus of the thermoplastic carrier substrate during the thermoforming (see the Note 1 above). Regarding claim 5, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to claim 1, wherein the electronic wiring is supported exclusively by the buffer layer, prior to and during thermoforming the stack (see Fig. 5, electrode 508 could be provided on the (top) face of the molded layer 106, para. [0157]). Regarding claim 6, Torvinen teaches the recited limitations with respect to claim 2. Torvinen further teaches, the method according to claim 2, wherein providing the backing layer of a structural support material comprises injection molding thermoplastic polymer composition in a space defined between an injection mould and a backward face of the thermoformed stack (feasible molding methods include e.g. injection molding, para. [0051, 0117]) and wherein the thermomechanical buffer layer has a modulus in a range of 0.02-2.5% of a storage modulus of the thermoplastic carrier substrate during thermoforming (see the Note 1 above). Regarding claim 7, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to claim 1, wherein the method comprises outgassing the thermomechanical buffer layer prior to the thermoforming (there is no air gap or generally gas volume, para. [0158], it which it is obvious that outgassing is performed). Regarding claim 8, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to claim 1, wherein the pressure during thermoforming is in a range of 30-70 bar (pressure applied on a target film… could be roughly over some 100 psi for a single layer film construction whereas it could be roughly over some 200 psi for laminated structures, para. [0116]) and wherein the temperature during thermoforming is in a range of 145-165°C (see para. [0116]). Regarding claim 9, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, the method according to according to claim 1, wherein the method further comprises, prior to applying the buffer layer, applying a graphic layer onto the face of carrier substrate defining a graphic pattern in accordance with a position of at least one of the electronic devices to be disposed (multilayer structure may thus incorporate one or more color/colored layers that optionally determine graphics such as text, pictures, symbols, logos, icons, patterns, etc.,… visual features such as graphical patterns or coloring may be provided via internal layers of the structure para. [0062-0064]). Regarding claim 20, Torvinen teaches the recited limitations with respect to claim 1. Torvinen further teaches, a car part (integration of electronics and related products may be…vehicle such as car interiors, para. [0004]) comprising the structural electronics module made by the method according to claim 1, wherein the carrier substrate is formed of a composition comprising polycarbonate (substrate film layer 102…polycarbonate, para. [0079]). Claim(s) 1 is alternatively rejected under 35 U.S.C. 103 as being unpatentable over Luijckx (WO 2010121674) in view of Torvinen (US 20180149321). [AltContent: textbox (electronic device)][AltContent: textbox (thermomechanical buffer layer)][AltContent: arrow][AltContent: arrow][AltContent: textbox (substrate)][AltContent: ] PNG media_image3.png 272 467 media_image3.png Greyscale Annotated Fig. 2, Luijckx. Regarding claim 1, Luijckx teaches, a method of manufacturing a thermoformed structural electronics module (Figs. 1 to 12) comprising one or more integrated electronic device (electronic component 12, Fig. 2, a module comprises several electronic components, these components are preferably connected so to each other, page 10, second paragraph), the method comprising: applying a thermomechanical buffer layer (linking layer 6, Fig. 2, linking layer 6,…Poly Vynil Butyral, page 15, fourth paragraph) along a face of a thermoplastic carrier substrate (substrate 7, substrate is a transparent or translucent polymer substrate layer…a polycarbonate layer, a plexiglass layer, page 21, first paragraph, plexiglass is polymethyl methacrylate); providing electronic wiring (conductive paths 2a, 2b, Fig. 2, several conductive paths 3, 3’, Fig. 10, conductive paths 2a, 2b can be electrically connected to a power supply and/or control device, page 15, second paragraph, page 19, third paragraph) and the one or more electronic device (electronic component 12) onto the buffer layer forming a stack wherein the electronic wiring and the at least one electronic device are disposed along a backward face of the buffer layer (see Fig. 2), opposite the carrier substrate; wherein the thermomechanical buffer layer (Poly Vynil Butyral layer) is comprised of a thermoplastic composition having a storage modulus that is within a range of 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate (polycarbonate substrate, alternatively, plexiglass substrate) during the thermoforming (see Note below). Luijckx does not teach thermoforming the stack to a mould under application of pressure and heat at a plasticizing condition of the carrier substrate and the buffer layer. However, Torvinen teaches, a method of manufacturing a thermoformed structural electronics module in Figs. 1 to 6 comprising an integrated electronic device, applying a thermomechanical buffer layer (material layer 106, thermoplastic polyurethane, para. 0095]) along a face of a thermoplastic carrier substrate (substrate layer 102, polycarbonate, para. [0079]); providing electronic wiring and the one or more electronic device (optical element 504, Fig. 5) onto the buffer layer forming a stack, and thermoforming the stack, including the carrier substrate and the buffer layer with the electronic device and corresponding electronic wiring provided thereon to a thermoformed stack in a mould under application of pressure and heat (pressure applied on a target film obtained either by pressing mechanically air into the mold,…the mold temperature about 20 to 95 degrees Celsius, e.g. about 80 degrees Celsius, para. [0116-0117]) at a plasticizing condition of the carrier substrate and the buffer layer. Though, Luijckx teaches a replaceable module, one of ordinary skill in the art would have thought that thermoforming the stack with the electronic device would improve its structural integrity. Therefore, in view of the teachings of Torvinen, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the thermoformed structural electronic module of Luijckx and to include a mold as Torvinen disclosed in para. [011-0117] so that it enables forming desired properties of the electronic module by properly fixing the thermoformed structural electronic module as Torvinen disclosed in para. [0047-0049]. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in molding the electronic module, or thermoforming the stack. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success. Note 2: Luijckx teaches a thermomechanical buffer layer 21 comprising polyvinyl butyral layer formed on a thermoplastic carrier substrate 7 comprising polycarbonate substrate, alternatively plexiglass substate, which is polymethyl methacrylate material. Instant application discloses in para. [0047-0049], the thermomechanical buffer layer 2 in Fig. 1A as polyvinyl butyral layer and thermoplastic carrier substrate 3 as polycarbonate material. Since Luijckx teaches identical composition as applicant discloses, the prior art composition would have the identical storage modulus as applicant claims and hence Luijckx meets the limitation “the thermomechanical buffer layer is comprised of a thermoplastic composition having a storage modulus that is within a range of 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate during the thermoforming”. If the prior art product is the same or substantially the same as the claimed product, the claimed properties or functions are presumed to be inherent. See MPEP § 2112.01. Conclusion Prior art Hanninen (US 11309676) teaches a method of manufacturing a thermoformed structural electronics module comprising integrated electronic device; applying a thermomechanical buffer layer; providing electronic wiring and the one or more electronic device onto the buffer layer forming a stack; followed by thermoforming the stack in a mold under application of pressure and heat at a plasticizing condition of the carrier substrate and the buffer layer. Prior art Hunt (US 20200163802) teaches a method of manufacturing a thermoformed structural electronics module comprising integrated electronic device; applying a thermomechanical buffer layer; providing electronic wiring and the one or more electronic device onto the buffer layer forming a stack; followed by thermoforming the stack in a mold under application of pressure and heat at a plasticizing condition of the carrier substrate and the buffer layer, and wherein the storage modulus that is within a range of 0.01% to 10% of a storage modulus of the thermoplastic carrier substrate. Prior art Yu (US 20080080181) teaches a method of manufacturing a thermoformed structural electronics module comprising integrated electronic device; applying a thermomechanical buffer layer; providing electronic wiring and forming a stack Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at (571) 272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSE K ABRAHAM/Examiner, Art Unit 3729
Read full office action

Prosecution Timeline

Jun 04, 2024
Application Filed
Jun 08, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+34.5%)
2y 9m (~8m remaining)
Median Time to Grant
Low
PTA Risk
Based on 360 resolved cases by this examiner. Grant probability derived from career allowance rate.

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