DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 2 recites the broad recitation “electromagnetic radiation in a substantially same or at least overlapping wavelength range”, and the claim also recites “in particular the infrared wavelength range” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
For the purposes of examination on the merits the examiner is interpreting “in particular the infrared wavelength range” as merely exemplary of the remainder of the claim, and therefore not required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6, 7, 9-11 and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dai et al. (United States Patent 11,140,352), hereinafter referenced as Dai.
Regarding claim 1, Dai discloses a pixel arrangement, comprising: a photosensitive stage being configured to generate electrical signals by converting electromagnetic radiation, wherein the photosensitive stage forms at least one sub-pixel of a first type comprising a photodiode that is configured to generate a low sensitivity signal (figure 2A exhibits SPD 216 which is a low sensitivity sub-pixel as disclosed at column 5 lines 4-15), and at least one sub-pixel of a second type comprising a photodiode that is configured to generate a high sensitivity signal (figure 2A exhibits LPDs 218, 220 and 222 which are higher sensitivity sub-pixel as disclosed at column 5 lines 4-15), and a sample-and-hold stage (figure 2B exhibits sample and hold stage 214A and 214B as disclosed at column 6 lines 21-33), wherein the sample-and-hold stage is electrically coupled to the photosensitive stage via a diffusion node (figures 2A and 2B show that the sub-pixels are connected to the sample and hold stage through FD node 232) and configured to sample and store the electrical signals from the photosensitive stage (column 6 line 41 – column 7 line 19 discloses the sample and hold operations of the sample and hold stages 214A and 214B).
Regarding claim 2, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses wherein the photodiode of the sub-pixel of the first type and the photodiode of the sub-pixel of the second type are configured to detect electromagnetic radiation in a substantially same or at least overlapping wavelength range, in particular the infrared wavelength range (column 4 lines 62-65 teaches that the sensor performs color imaging, the only difference between the subpixels are their size and the presence of a ND filter which only affects sensitivity and does not change the wavelengths detected, therefore it is apparent that the sub-pixels detect light in a substantially same wavelength range).
Regarding claim 4, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses a filter layer between the incident electromagnetic radiation and the sub-pixel of the first type, wherein the filter layer is configured to reduce an intensity of the electromagnetic radiation (figure 2A exhibits wherein the first photodiode 216 is covered with a ND filter 246 as disclosed at column 5 lines 31-43).
Regarding claim 6, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses a first transfer gate configured to transfer the low sensitivity signal of the sub-pixel of the first type to the diffusion node (figure 2A exhibits a first transfer gate 224 as disclosed at column 5 lines 15-31), a second transfer gate configured to transfer the high sensitivity signal of the sub-pixel of the second type to the diffusion node (figure 2A exhibits transfer gate 226 as disclosed at column 5 lines 15-31), and a reset switch configured to reset the diffusion node between the transfers of the low sensitivity signal and the high sensitivity signal (figure 2A exhibits reset transistor 238 as disclosed at column 6 lines 4-10).
Regarding claim 7, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses an amplifying stage electrically connected between the diffusion node and the sample-and-hold stage and being configured to amplify the electrical signals from the photosensitive stage (figure 2A exhibits source follower transistor 234 as disclosed at column 5 lines 59-67).
Regarding claim 9, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses wherein the sample-and-hold stage further comprises a first pair of capacitors (figure 2B exhibits capacitors C00 and C01) and a second pair of capacitors (figure 2B exhibits capacitors C10 and C11), wherein one capacitor of the first pair of capacitors is configured to store a reset level before readout (column 8 lines 47-56 teaches storing a reset level in capacitor C00), and wherein another capacitor of the first pair of capacitors is configured to store the high sensitivity signal before readout (column 9 lines 5-15 disclose storing a LPD signal in capacitor C01), and wherein one capacitor of the second pair of capacitors is configured to store a further reset level before readout (column 9 lines 22-31 teaches that capacitor C10 stores a reset level), and wherein another capacitor of the second pair of capacitors is configured to store the low sensitivity signal before readout (column 10 lines 18-31 teaches that a SPD signal is stored in capacitor C11).
Regarding claim 10, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses a dual conversion gain stage comprising a further capacitor electrically coupled to the diffusion node via a gain switch and configured to increase a capacitance of the diffusion node (figure 2A exhibits DFD transistor 240 and capacitor 242 as disclosed at column 10 lines 40-43).
Regarding claim 11, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses an overflow capacitor electrically coupled to the photodiode of the sub-pixel of the first type and configured to store excess charge carriers from said photodiode (figure 2A exhibits overflow capacitor 242 which is connected to photodiode 216 through transistor 244 and is a lateral overflow capacitor as disclosed at column 5 lines 43-57).
Regarding claim 15, Dai discloses an image sensor (figure 1 exhibits an image sensor) comprising the pixel arrangement according to one of claim 1 (see claim 1).
Regarding claim 16, Dai discloses a method for operating a pixel arrangement, the method comprising: generating, by a photosensitive stage comprising at least one sub-pixel of a first type and at least one sub-pixel of a second type (figures 2A exhibits a photosensitive stage with a SPD pixel 216 and LPD pixels 218, 220 and 220), electrical signals by converting electromagnetic radiation (figure 3A exhibits a timing diagram in which LPD photodiodes generate electrical signals during an exposure period between the timing of RST being high and TX1 as disclosed at column 8 lines 57-61 and SPD photodiodes generate electrical signals during an exposure period between a second timing of RST and TX0 as disclosed at column 10 lines 18-23), wherein a low sensitivity signal is generated by a photodiode of the sub-pixel of the first type (column 5 lines 4-15 teaches that SPD is a small photodiode and therefore has a lower sensitivity compared to a larger photodiode), and wherein a high sensitivity signal is generated by a photodiode of the sub-pixel of the second type (column 5 lines 4-15 teaches that LPDs are large photodiodes and therefore have a higher sensitivity compared to the smaller photodiode), sampling and storing, by a sample-and-hold stage being coupled to the photosensitive stage via a diffusion node (figures 2A and 2B show that the photodiodes are connected to the sample and hold stages 214A and 214B via floating diffusion node 232), the electrical signals from the photosensitive stage (column 9 lines 5-15 disclose storing a LPD signal in capacitor C01 and column 10 lines 18-31 teaches that a SPD signal is stored in capacitor C11).
Regarding claim 17, Dai discloses the method of claim 16, in addition, Dai discloses transferring, by a first transfer gate, the low sensitivity signal of the sub-pixel of the first type to the diffusion node (figure 3A exhibits a timing diagram in which SPD photodiodes generate electrical signals during an exposure period between a second timing of RST and TX0 as disclosed at column 10 lines 18-23), transferring, by a second transfer gate, the high sensitivity signal of the sub-pixel of the second type to the diffusion node (figure 3A exhibits a timing diagram in which LPD photodiodes generate electrical signals during an exposure period between the timing of RST being high and TX1 as disclosed at column 8 lines 57-61), and resetting, by a reset switch, the diffusion node between the transfers of the low sensitivity signal and the high sensitivity signal (figure 3A exhibits the reset for SPD, the second time the RST signal is pulsed which resets the floating diffusion node 232).
Regarding claim 18, Dai discloses the method according to claim 16, in addition, Dai discloses sampling and storing a reset level on a capacitor of a first pair of capacitors of the sample-and-hold-stage (column 8 lines 47-56 teaches storing a reset level in capacitor C00), sampling and storing the high sensitivity signal on another capacitor of the first pair of capacitors (column 9 lines 5-15 disclose storing a LPD signal in capacitor C01), sampling and storing a further reset level on a capacitor of a second pair of capacitors of the sample-and-hold-stage (column 9 lines 22-31 teaches that capacitor C10 stores a reset level), sampling and storing the low sensitivity signal on another capacitor of the second pair of capacitors (column 10 lines 18-31 teaches that a SPD signal is stored in capacitor C11), and reading out, by a readout stage, the reset level, the further reset level, the low sensitivity signal and the high sensitivity signal (column 12 lines 20-41 teach performing readout and AD operations on each of the stored signals).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Dai in view of Naruse et al. (United States Patent Application Publication 2011/0141333), hereinafter referenced as Naruse.
Regarding claim 3, Dai discloses the pixel arrangement according to claim 1, however, Dai fails to disclose wherein the photosensitive stage and the sample-and-hold stage are arranged at or on a main surface of a semiconductor substrate, and wherein the photosensitive stage is illuminated by electromagnetic radiation from a back surface of the semiconductor substrate.
Naruse is a similar or analogous system to the claimed invention as evidenced Naruse teaches an image sensor wherein the motivation of allowing pixels to be miniaturized and to improving the sensitivity of the pixels would have prompted a predictable variation of Dai by applying Naruse’s known principal of forming pixel and corresponding circuits at or on a main surface of a semiconductor substrate (figure 6 exhibits wherein photodiodes PD1 and PD2 and a scan circuit are formed at a signal scan circuit side as disclosed at paragraph 68) and wherein the photosensitive stage is illuminated by electromagnetic radiation from a back surface of the semiconductor substrate (figure 6 exhibits wherein the photodiodes are back side illuminated as disclosed at paragraph 24).
In view of the motivations such as allowing pixels to be miniaturized and to improving the sensitivity of the pixels one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dai in view of Mabuchi (United States Patent Application Publication 2009/0251556).
Regarding claim 5, Dai discloses the pixel arrangement according to claim 1, however, Dai fails to disclose wherein an integration time of the photodiode of the sub-pixel of the first type is shorter than an integration time of the photodiode of the sub-pixel of the second type.
Mabuchi is a similar or analogous system to the claimed invention as evidenced Mabuchi teaches an imaging device wherein the motivation of providing pixel signals with different sensitivities for high dynamic range imaging would have prompted a predictable variation of Dai by applying Mabuchi’s known principal of setting an integration time of a low sensitivity pixel to be less than that of a higher sensitivity pixel (paragraph 63 teaches using a short exposure time for low-sensitivity pixels).
In view of the motivations such as providing pixel signals with different sensitivities for high dynamic range imaging one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claims 8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over of Dai in view of Lee et al. (United States Patent Application Publication 2022/0094864), hereinafter referenced as Lee.
Regarding claim 8, Dai discloses the pixel arrangement according to claim 1, in addition, Dai discloses wherein the sample-and-hold stage comprises a first pair of capacitors (figure 2B exhibits capacitors C00 and C01), wherein one capacitor of the first pair of capacitors is configured to store a reset level before readout (column 8 lines 47-56 teaches storing a reset level in capacitor C00), and wherein another capacitor of the first pair of capacitors is configured to store the high sensitivity signal before readout (column 9 lines 5-15 disclose storing a LPD signal in capacitor C01). However, Dai fails to disclose wherein the diffusion node is configured to store the low sensitivity signal before readout.
Lee is a similar or analogous system to the claimed invention as evidenced Lee teaches an image sensor wherein the motivation of minimizing readout times would have prompted a predictable variation of Dai by applying Lee’s known principal of storing a pixel signal from a second photodiode in a floating diffusion node prior to readout (paragraphs 131 and 132 teach storing a first photodiode signal and a reset signal in a first pair of capacitors and storing a second photodiode signal in a diffusion node FD).
In view of the motivations such as minimizing readout times one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 19, Dai discloses the method according to claim 16, in addition, Dai discloses sampling and storing a reset level on a capacitor of a first pair of capacitors of the sample-and-hold-stage (column 8 lines 47-56 teaches storing a reset level in capacitor C00), sampling and storing the high sensitivity signal on another capacitor of the first pair of capacitors (column 9 lines 5-15 disclose storing a LPD signal in capacitor C01). However, Mo fails to disclose storing the low sensitivity signal on the diffusion node, reading out, by a readout stage, the reset level, the low sensitivity signal and the high sensitivity signal.
Lee is a similar or analogous system to the claimed invention as evidenced Lee teaches an image sensor wherein the motivation of minimizing readout times would have prompted a predictable variation of Dai by applying Lee’s known principal of storing a pixel signal from a second photodiode in a floating diffusion node prior to readout (paragraphs 131 and 132 teach storing a first photodiode signal and a reset signal in a first pair of capacitors and storing a second photodiode signal in a diffusion node FD) and reading out the reset and each signal (paragraphs 131 and 133 teach outputting the signals to the column line CL).
In view of the motivations such as minimizing readout times one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Dai in view of Mo et al. (United States Patent Application Publication 2018/0227516), hereinafter referenced as Mo.
Regarding claim 12, Dai discloses the pixel arrangement according to claim 1, wherein one sub-pixel of the first type and three sub-pixels of the second type are arranged in an array (figure 1 exhibits array of pixels 104, figure 2A exhibits each pixel including one SPD sub-pixel and three LPD sub-pixels). However, Dai fails to disclose where the array is a 2x2 array.
Mo is a similar or analogous system to the claimed invention as evidenced Mo teaches an imaging device wherein the motivation of minimizing the space between shared components in a pixel would have prompted a predictable variation of Dai by applying Mo’s known principal of arranging sub-pixels in a 2x2 array (figure 5 exhibits sub-pixels arranged in a 2x2 array).
In view of the motivations such as minimizing the space between shared components in a pixel one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dai in view of Mo and further in view of Kaneko et al. (United States Patent Application Publication 2018/0146148), hereinafter referenced as Kaneko.
Regarding claim 13, Dai in view of Mo discloses a pixel matrix comprising four pixel arrangements according to claim 12, wherein the pixel arrangements are arranged in a 2 x 2 matrix (figure 5 of Mo exhibits wherein the pixels are arranged in a 2x2 matrix). However, Dai fails to disclose wherein the sub-pixels of the first type are arranged adjacent to each other in the center of the 2 x 2 matrix, and wherein the sub-pixels of the second type surround the sub-pixels of the first type in lateral directions.
Kaneko is a similar or analogous system to the claimed invention as evidenced Kaneko teaches an image sensor wherein the motivation of maintaining a Bayer color array pattern would have prompted a predictable variation of Dai by applying Kaneko’s known principal of providing an array such that sub-pixels of the first type are arranged adjacent to each other in the center of the 2 x 2 matrix, and wherein the sub-pixels of the second type surround the sub-pixels of the first type in lateral directions (figure 5 exhibits wherein smaller sub-pixels are surrounded by larger sub-pixels as disclosed at paragraph 113).
In view of the motivations such as maintaining a Bayer color array pattern one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Dai in view of Mo and further in view of Kono (United States Patent Application Publication 2022/0123034).
Regarding claim 14, Dai in view of Mo discloses a pixel matrix comprising four pixel arrangements according to claim 12, wherein the pixel arrangements are arranged in a 2 x 2 matrix (figure 5 of Mo exhibits wherein the pixels are arranged in a 2x2 matrix). However, Dai fails to disclose wherein the matrix is in a same orientation, such that, in lateral directions, the sub-pixels of the first type are separated from each other by a respective sub-pixel of the second type.
Kono is a similar or analogous system to the claimed invention as evidenced Kono teaches an image sensor wherein the motivation of maintaining a Bayer color array pattern would have prompted a predictable variation of Dai by applying Kono’s known principal of providing an array such that the matrix is in a same orientation, such that, in lateral directions, the sub-pixels of the first type are separated from each other by a respective sub-pixel of the second type (figure 8 exhibits 2x2 matrices of pixels which are arranged in a same orientation such that each low sensitivity pixel is arranged in a bottom right of a matrix and separated by a pixel of a higher sensitivity).
In view of the motivations such as maintaining a Bayer color array pattern one of ordinary skill in the art would have implemented the claimed variation of the prior art system of Dai.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Dai.
Regarding claim 20, Lee discloses a pixel arrangement, comprising: a photosensitive stage being configured to generate electrical signals by converting electromagnetic radiation (figure 15A exhibits a pair of photodiodes PDL and PDR), wherein the photosensitive stage forms at least one sub-pixel of a first type comprising a photodiode (figure 15A exhibits a first sub-pixel PXL comprising a first photodiode PDL), and at least one sub-pixel of a second type comprising a photodiode (figure 15A exhibits a second sub-pixel PXR comprising a second photodiode PDR), a sample-and-hold stage, wherein the sample-and-hold stage is electrically coupled to the photosensitive stage via a diffusion node and configured to sample and store the electrical signals from the photosensitive stage (figure 15A exhibits a sample and hold stage comprising transistors SAMP1, SAMP2 and capacitors C1 and C2 which is connected to the photodiodes via floating diffusion node FD), a readout stage comprising one or more select gates (figure 15A exhibits a readout stage including select transistor SX), wherein the readout stage electrically connects the pixel arrangement to a column bus (figure 15A exhibits wherein the select transistor SX connects the pixel arrangement to column bus line CL), an amplifying stage electrically connected between the diffusion node and the sample-and-hold stage and being configured to amplify the electrical signals from the photosensitive stage (figure 15A exhibits source follower transistor SF1 which amplifies the signal at the floating diffusion node and outputs the amplified signal to the sample and hold stage), and a further amplifying stage electrically connected between the sample-and-hold stage and the readout stage (figure 15A exhibits source follower transistors SF2 which amplifies the signal from the sample and hold stage and outputs the amplified signal to the column line CL via select transistor SX). However, Lee fails to disclose that first type is configured to generate a low sensitivity signal, and the second type is configured to generate a high sensitivity signal.
Lee discloses a pixel with sub-pixels in which each sub-pixel is the same. Dai discloses a pixel with sub-pixels including at least one sub-pixel of a first type comprising a photodiode that is configured to generate a low sensitivity signal, and at least one sub-pixel of a second type comprising a photodiode that is configured to generate a high sensitivity signal (figure 2A exhibits a photosensitive stage of a pixel cell which includes a low sensitivity photodiode 216 and high sensitivity photodiodes 218-222 as disclosed at column 5 lines 4-15). Because both Lee and Dai teach a pixel including sub-pixels, it would have been obvious to a person having ordinary skill in the art to substitute the sub-pixels disclosed by Dai for the sub-pixels disclosed by Lee to achieve the predictable result of creating a pixel which can capture a high dynamic range image.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Citation of Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Oishi (United States Patent Application Publication 2023/0269503) teaches a pixel array.
Huang (United States Patent Application Publication 2020/0112697) teaches a pixel array.
Lyu et al. (United States Patent 9,666,631) teaches a HDR pixel array.
Johnson et al. (United States Patent Application Publication 2016/0255289) teaches a HDR pixel array.
Yamazaki et al. (United States Patent Application Publication 2012/0075507) teaches a pixel array.
Okita et al. (United States Patent Application Publication 2011/0157441) teaches a pixel array.
Hashimoto et al. (United States Patent Application Publication 2011/0157441) teaches a CDS circuit for a pixel array.
Conclusion
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JASON A. FLOHRE
Patent Examiner
Art Unit 2637
/JASON A FLOHRE/ Patent Examiner, Art Unit 2637