DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai (US 2015 0288365).
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With respect to claim 1, Lai (US 2015 0288365) discloses a transistor circuit comprising: a first transistor (Mn1) configured to: receive, at a source of the first transistor, an input signal (Vss) as an input of the first transistor; and output a first output signal (a1); and a second transistor (Mn2) configured to: operate, based on a bias to the second transistor (bias at Sinb), in a complementary manner with respect to the first transistor; receive the input signal (Vss) as an input of the second transistor and output a second output signal (a2), that is in a reverse polarity with respect to the first output signal (a1).
With respect to claim 4, Lai discloses the transistor circuit according to claim 1, further comprising a voltage conversion circuit (Mp1 and Mp2) that includes a first input terminal (at gate of Mp2) configured to receive the first output signal (at a1) as a first input to the voltage conversion circuit; and a second input terminal (at gate of Mp1) configured to receive the second output signal (at a2) as a second input to the voltage conversion circuit; wherein the voltage conversion circuit is configured to: convert based on a transconductance of the first transistor a first current from the first transistor into a first voltage output the first voltage from the first input terminal, convert based on a transconductance of the second transistor, a second current from the second transistor into a second voltage; and output the second voltage from the second input terminal.
Claim(s) 1-6 and 9-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jasa (US 20090251227).
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With respect to claim 1, Jasa (US 20090251227) discloses a transistor circuit comprising: a first transistor (M3) configured to: receive, at a source of the first transistor, an input signal (Vdd) as an input of the first transistor; and output a first output signal (Io); and a second transistor (M4) configured to: operate, based on a bias to the second transistor (bias at gate), in a complementary manner with respect to the first transistor; receive the input signal (Vdd) as an input of the second transistor and output a second output signal (Io’), that is in a reverse polarity with respect to the first output signal (Io).
With respect to claim 2, Jasa discloses the transistor circuit according to claim 1, wherein each of the first output signal (Io) and the second output signal (Io’) is a differential output signal.
With respect to claim 3, Jasa discloses the transistor circuit according to claim 1, wherein the first transistor (M3) includes a first terminal, a second terminal, and a first control terminal (at gate), the first control terminal is configured to control a current that flows between the first terminal and the second terminal, the second transistor (M4) includes a third terminal, a fourth terminal, and a second control terminal (at gate), the second control terminal is configured to control a current that flows between the third terminal and the fourth terminal, the first output signal is output from the first terminal, the second output signal is output from the third terminal, the second terminal is the source of the first transistor, and the second control terminal is configured to receive the input signal (Vdd is received at the control terminal when the transistor M4 is on) .
With respect to claim 4, Jasa discloses the transistor circuit according to claim 1, further comprising a voltage conversion circuit (M1 and M2) that includes a first input terminal (at drain of M1) configured to receive the first output signal (at drain) as a first input to the voltage conversion circuit; and a second input terminal (at drain of M2) configured to receive the second output signal (at drain) as a second input to the voltage conversion circuit; wherein the voltage conversion circuit is configured to: convert based on a transconductance of the first transistor a first current from the first transistor into a first voltage output the first voltage from the first input terminal, convert based on a transconductance of the second transistor, a second current from the second transistor into a second voltage; and output the second voltage from the second input terminal.
With respect to claim 5, Jasa discloses the transistor circuit according to claim 3, wherein the first transistor is a first field effect transistor, the second transistor is a second field effect transistor (M3 and M4 are FETs) the first terminal is a drain of the first field effect transistor, the third terminal is a drain of the second field effect transistor (M3 and M4 are FETs), the first control terminal is a gate of the first field effect transistor, the second control terminal is a gate of the second field effect transistor and the fourth terminal is a source (the FETs in this configuration would have sources at the top and drains at the bottom for the PNP configuration) of the second field effect.
With respect to claim 6, Jasa discloses the transistor circuit according to claim 3, further comprising a bias circuit (M5-M7) configured to: apply a first bias voltage (through M1) to the first control terminal of the first transistor; and apply a second bias voltage (through M2) to the fourth terminal of the second transistor, wherein based on the applied first bias voltage and the applied second bias voltage a first voltage between the second terminal and the first control terminal is equal to a second voltage between the fourth terminal and the second control terminal, the first voltage is at a time of generation of a transconductance of the first transistor, and the second voltage is at a time of generation of a transconductance of the second transistor (Vgd of M3 would equal Vgd of M4 in magnitude).
With respect to claim 9, Jasa discloses the transistor circuit according to claim 3, wherein each of the first transistor and the second transistor is a P-channel field effect transistors (M3 and M4 are P channel fets); the input signal is at a Complementary Metal Oxide Semiconductor (CMOS) level between a ground potential (GND) and a first power supply potential (VDD) the first control terminal is connected to the first ground potential (via M1), and the fourth terminal is connected to a second power supply potential (via M4).
With respect to claim 10, Jasa discloses the transistor circuit according to claim 3, wherein: the input signal is at a level different from a Complementary Metal Oxide Semiconductor (CMOS) level; and each of the first control terminal (at gate of M3) and the fourth terminal (between M2 and M4) are connected to a common potential (both would have the same or common magnitude).
With respect to claim 11, Jasa discloses the transistor circuit according to claim 10, wherein the common potential is variable (high or low varies with input).
With respect to claim 12, Jasa discloses the transistor circuit according to claim 10, further comprising a bias generation unit (M5-M7) configured to generate the common potential based on the input signal (at gate of M4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jasa (US 20090251227) in view of Berens (US 20080042770).
With respect to claim 8, Jasa discloses the transistor circuit according to claim 3, the input signal is at a Complementary Metal Oxide Semiconductor (CMOS) level between a first ground potential (gnd) and a power supply potential (Vdd), the first control terminal is connected to the power supply potential, and the fourth terminal is connected to a second ground potential but fails to dsiclsoe wherein each of the first transistor and the second transistor is an N-channel field effect transistor (M3 and M4),
Berens teaches the interchanging of a PMOS transistor for an NMOS transistor-based CMOS circuits such as amplifiers [see 0036]. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to switch substitute P transistors for N transistors for the purpose of saving area as a PMOS takes more surface area than an NMOS, for speed and efficiency as NMOS transistors are generally faster.
Allowable Subject Matter
Claim 7 and 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 7, the prior art of record fails to suggest or disclose the transistor circuit according to claim 3, further comprising a bias circuit wherein each of the first transistor and the second transistor is a field effect transistor and the bias circuit is configured to bias each of a back gate of the first transistor and a back gate of the second transistor.
Here although the back gate is biased by VDD, the back gate of M3 and M4 is not biased by the bias circuit of M5-M7.
Response to Arguments
Applicant’s arguments, see pgs. 1-5, filed 12/2/2025, with respect to the rejection(s) of claim(s) 1-6 and 9-12 under Jasa and Lai have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the new interpretation of Jasa and Lai.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849