Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, requires the specification to be written in “full, clear, concise, and exact terms.” The specification is replete with terms which are not clear, concise and exact. The specification should be revised carefully in order to comply with 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112. Examples of some unclear, inexact or verbose terms used in the specification are: "sorts the flight information in ascending or descending order by the bin numbers including the one to which the flight information occurred this time belongs", "When new flight information occurs, the memory processing circuit causes the memory circuit for storage to function as the memory circuit for reference, and compares the bin number read out from the memory circuit for reference with the bin number to which the new flight information belongs.", "As shown in Figs 1 and 2," should really specify this is the description for the Figure 2 drawing, the representative value and distance value circuits 70 and 80 are mentioned in the middle of the description of Figure 3 yet are not present. While not specifically stated to be a part of Figure 3 it is still confusing, .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors. Examiner notes that each claim will still be examined based on the simplest interpretation of said claim and the interpretation will be stated in the individual claim rejections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102Niclass (US 20190018119 A1) as being anticipated by Niclass (US 20190018119 A1).
Regarding claim 1, the examiner interprets a histogram generating circuit that generates a histogram based on respective flight information that is a time of flight or a flight distance from an emission time point of measurement light repeatedly emitted at predetermined periods to a detection time point of reflected light for respective measurement light, as stated. Niclass discloses such, “The bottom plot in FIG. 3 shows a histogram giving the counts of measurements of times of flights of reflected light pulses detected over the sequence of multiple PRIs. “ (Paragraph 0058) and “The light pulses are separated by an interval of time termed a pulse repetition interval (PRI) 304.” (Paragraph 0054). See Figure 3 as well. Examiner interprets the histogram showing a cumulative frequency of the flight information distributed in a preset measurement range as stated. Niclass discloses such, see Figure 3 and “The bottom plot in FIG. 3 shows a histogram giving the counts of measurements of times of flights of reflected light pulses detected over the sequence of multiple PRIs. “ (Paragraph 0058) and “The light pulses are separated by an interval of time termed a pulse repetition interval (PRI) 304.” (Paragraph 0054). Examiner interprets the histogram generating circuit comprising: a memory circuit configured to store the histogram as stated. Niclass discloses such, “For memory efficiency, the histogram of each light sensing pixel may be expanded by one memory bin that can be used to store the E−L difference.” (Paragraph 0107) and see the entirety of Paragraph 0107 and Figure 13 as well. Examiner interprets a memory processing circuit configured to associate a bin number for identifying each bin obtained by splitting the measurement range into a plurality of divisions individually in order based on the flight information with the flight information contained in each bin and the cumulative frequency, and store the bin number, the flight information, and the cumulative frequency in the memory circuit as that the time intervals are divided into smaller time bins that contain flight information. These bins are then added together in the histogram over multiple emitted pulses based on Figures 4 and 5 in the drawings to create the histogram and create the cumulative frequency. Niclass discloses such, Figure 3 and “The bottom plot in FIG. 3 shows a histogram giving the counts of measurements of times of flights of reflected light pulses detected over the sequence of multiple PRIs. “ (Paragraph 0058) and “The light pulses are separated by an interval of time termed a pulse repetition interval (PRI) 304.” (Paragraph 0054) as well as “The horizontal axis 306 shows the duration of a single PRI subdivided into the N successive discrete time intervals 312, each of duration PRI/N. The vertical axis 308 is the number of counts held in a block of N memory locations (or “bins”), each bin corresponding to a respective one of the discrete time intervals 312.” (Paragraph 0058).
Regarding claim 2, examiner interprets the histogram generating circuit according to claim 1, wherein when the flight information occurs, the memory processing circuit reads out the bin number stored in the memory circuit, sorts the flight information in ascending or descending order by the bin numbers including the one of the bin to which the flight information occurred this time belongs, and stores the bin numbers, the flight information, and the cumulative frequency in the memory circuit as that the memory processing circuit sorts the flight information by bin numbers, as such sorts the bin numbers based on what time interval they cover. For example bin 1 covers the first 0.5 ms then bin 2 covers the second 0.5 ms, and bin 3 covers the next 0.5 ms, so the order would be bin 1, bin 2, and bin 3 or bin 3, bin 2, and bin 1. Niclass discloses the histogram generating circuit according to claim 1, see claim 1 rejection. Niclass discloses the claim based on the examiners interpretation, “The horizontal axis 306 shows the duration of a single PRI subdivided into the N successive discrete time intervals 312, each of duration PRI/N.” (Paragraph 0058) and see Figure 3.
Regarding claim 3, examiner interprets the claim as stated. Niclass discloses the histogram generating circuit according to claim 1, see claim 1 rejection. Niclass discloses that as the memory circuit, a memory circuit for reference to grasp an already stored bin number and a memory circuit for storage to store bin numbers including a new bin number and the cumulative frequency when the flight information occurs, “The front end circuitry 602 may be linked with both Early-Late detector 606 and with a memory 608 that can be configured to record the histograms formed for each of the pixels in the path 502 swept by the beam. At the end of each sweep of the beam, the results are processed by read out circuitry 610. “ (Paragraph 0080) and Figure 6. Niclass discloses that the memory processing circuit is configured to switch functions of the memory circuit for reference and the memory circuit for storage for each occurrence of the flight information; read out a bin number stored in the memory circuit for reference, “The front end circuitry 602 may be linked with both Early-Late detector 606 and with a memory 608 that can be configured to record the histograms formed for each of the pixels in the path 502 swept by the beam. At the end of each sweep of the beam, the results are processed by read out circuitry 610. “ (Paragraph 0080). Inherently the circuitry must be able to switch functions to be able to record the histograms and readout the results. Niclass discloses that the memory processing circuit is configured to sort the flight information in ascending or descending order by the bin numbers including the one to which the flight information occurred this time belongs; and store the bin numbers, the flight information, and the cumulative frequency in the memory circuit for storage, see claim 2 rejection.
Regarding claim 4, examiner interprets the claim as stated. Niclass discloses the histogram generating circuit according to claim 3, see claim 3 rejection. Niclass discloses that the memory processing circuit stores the bin number, the flight information, and the cumulative frequency in the memory circuit for storage without switching the functions of the memory circuit for reference and the memory circuit for storage at first occurrence of the flight information, “The front end circuitry 602 may be linked with both Early-Late detector 606 and with a memory 608 that can be configured to record the histograms formed for each of the pixels in the path 502 swept by the beam. At the end of each sweep of the beam, the results are processed by read out circuitry 610.“ (Paragraph 0080). Inherently to be able to record and readout the results of each sweep, the circuity discloses by Niclass must not switch it’s functions during the first time of flight detection.
Regarding claim 5, examiner interprets the claim as stated. Niclass discloses the histogram generating circuit according to claim 1, see claim 1 rejection. Niclass discloses a FIFO-type memory circuit,wherein the FIFO-type memory circuit includes a write circuit configured to store the flight information in synchronization with occurrence of the flight information, “The front end circuitry 602 may be linked with both Early-Late detector 606 and with a memory 608 that can be configured to record the histograms formed for each of the pixels in the path 502 swept by the beam.” (Paragraph 0080) and Figure 6. Niclass discloses a readout circuit configured to read out and output the flight information to the memory processing circuit asynchronously to the occurrence of the flight information, “At the end of each sweep of the beam, the results are processed by read out circuitry 610.” (Paragraph 0080) and Figure 6.
Regarding claim 6, examiner interprets the claim as stated. Niclass discloses the histogram generating circuit according to claim 5, see claim 5 rejection. Niclass discloses the write circuit is configured to store dummy data indicating an end of output of the flight information in one period in the FIFO-type memory circuit every time the output of the flight information ends at the predetermined periods, “A blanking interval 702 can occur at the end of each frame for read out and other operations” (Paragraph 0081). Niclass discloses that the readout circuit is configured to output a signal indicating an end of output of the flight information in one period every time when reading out the dummy data, “A blanking interval 702 can occur at the end of each frame for read out and other operations, such as moving the beam-steering element 408 (e.g., a mirror) for the next scan.” (Paragraph 0081). See Figure 7 as well.
Regarding claim 7, examiner interprets a representative value calculation circuit configured to calculate a representative value of the flight information for the object from the flight information that is distributed in the bin of the bin number where the frequency reaches a predetermined histogram threshold based on the histogram as the value being calculated being based on the bin with the highest peak. Examiner interprets the rest of the claim language as stated. Niclass discloses a light emitting element configured to emit pulsed measurement light, “The light emitting depth sensors operate by emitting light pulses, such as laser light pulses, into the field of view and determining the times until the reflected pulses are received on a light detector.” (Paragraph 0038). Niclass discloses a plurality of photon counting type light receiving elements configured to detect reflected light from an object for the measurement light, “In embodiments of such systems in which the detector 202 has pixels that include SPADs to detect light, a SPAD may be activated by being placed into a reversed biased state, such as by accompanying transistors or other circuitry. In particular, a SPAD is operated in the avalanche region of reverse bias. When one or more photons enter the SPAD, charge carriers are created that migrate to an electrode.” (Paragraph 0047). Niclass discloses an adder circuit configured to add voltage pulses output from the respective light receiving elements, “When one or more photons enter the SPAD, charge carriers are created that migrate to an electrode. In so doing, they cause a cascade or “avalanche” that increases the number of charge carriers leading to a measurable current spike.” (Paragraph 0047) and “The vertical axis 308 is the number of counts held in a block of N memory locations (or “bins”), each bin corresponding to a respective one of the discrete time intervals 312. The TDC can comprise a timer and circuitry to rapidly address and increment a counter for the bin corresponding to the particular discrete time subinterval during which a light pulse is detected by the SPAD pixel. In the example shown, during the third PRI, when the reflected light pulse 316 is detected, the TDC measures the TOF.sub.1 314A and increments the corresponding count 314B in the respective bin in the histogram.” (Paragraph 0058). Also see Figure 3. Niclass discloses a flight information calculation circuit configured to calculate, as flight information, time from an emission time point of the measurement light to a time point at which a sum from the adder circuit reaches a predetermined addition threshold, or a distance corresponding to the time, “The processing device 108 may cause the light emitter 102 to emit light towards the object 106 (emitted light represented by arrow 110). The light reflected from the object 106 and/or the scene may then be detected by the detector 104 (reflected light represented by arrow 112). The processing device 108 receives the output signals from the detector 104 and processes the output signals to determine one or more characteristics associated with the reflected light, the object 106, and/or the scene. The processing device 108 may obtain estimates of the presence and range (distance) to the object 106 using the one or more characteristics of the emitted and reflected light.” (Paragraph 0044). Niclass discloses a histogram generating circuit according to claim 1, configured to generate a histogram showing a cumulative frequency of the flight information distributed in a preset measurement range based on the flight information calculated by the flight information calculation circuit when the measurement light is repeatedly emitted at predetermined periods, see claim 1 rejection. Niclass discloses a representative value calculation circuit configured to calculate a representative value of the flight information for the object from the flight information that is distributed in the bin of the bin number where the frequency reaches a predetermined histogram threshold based on the histogram, “The peak 322 may be above the background noise level 324 of detected light pulses not arising as reflections of emitted light pulses. The discrete time subinterval corresponding to the peak 322 can then be taken as the TOF and used to obtain the range to the object.” (Paragraph 0059). Niclass discloses a distance calculation circuit configured to calculate a distance to the 34 object based on the representative value of the flight information calculated by the representative value calculation circuit, “The processing device 108 may cause the light emitter 102 to emit light towards the object 106 (emitted light represented by arrow 110). The light reflected from the object 106 and/or the scene may then be detected by the detector 104 (reflected light represented by arrow 112). The processing device 108 receives the output signals from the detector 104 and processes the output signals to determine one or more characteristics associated with the reflected light, the object 106, and/or the scene. The processing device 108 may obtain estimates of the presence and range (distance) to the object 106 using the one or more characteristics of the emitted and reflected light.” (Paragraph 0044).
Regarding claim 8, claim 8 is rejected under the same reasoning as claim 1. See claim 1 rejection.
Regarding claim 9, the claim will be interpreted as stated. Niclass discloses a reflected light detection step of detecting reflected light from an object for pulsed measurement light emitted from a light emitting element using a plurality of photon counting type light receiving elements, “ The light emitter 102 is positioned to emit light towards an object (or “target”) 106, and the detector 104 is situated to detect light reflected from the object 106.” (Paragraph 0042) and “In embodiments of such systems in which the detector 202 has pixels that include SPADs to detect light, a SPAD may be activated by being placed into a reversed biased state, such as by accompanying transistors or other circuitry. In particular, a SPAD is operated in the avalanche region of reverse bias. When one or more photons enter the SPAD, charge carriers are created that migrate to an electrode.” (Paragraph 0047). Niclass discloses a flight information calculation step of calculating, as flight information, a time from an emission time point of the measurement light to a time point at which a sum of voltage pulses output from the respective light receiving elements reaches a predetermined addition threshold, or a distance corresponding to the time, see claim 7 rejection. Niclass discloses a histogram generation step of performing a histogram generation method according to claim 8, generating a histogram showing a cumulative frequency of the flight information distributed in a preset measurement range based on the flight information calculated in the flight information calculation step when the measurement light is repeatedly emitted at predetermined periods, see claim 8 rejection. Niclass discloses a representative value calculation step of calculating a representative value of the flight information for the object from the flight information distributed in the bin of the bin number where the frequency reaches a predetermined histogram threshold based on the histogram, see claim 7 rejection. Niclass discloses a distance calculation step of calculating a distance to the object based on the representative value of the flight information calculated in the representative value calculation step, see claim 7 rejection.
Regarding claim 10, claim is rejected under the same reasoning as claim 2 and claim 7. See both rejections.
Regarding claim 11, claim is rejected under the same reasoning as claim 3 and claim 7. See both rejections.
Regarding claim 12, claim is rejected under the same reasoning as claim 4 and claim 7. See both rejections.
Regarding claim 13, claim is rejected under the same reasoning as claim 5 and claim 7. See both rejections.
Regarding claim 14, claim is rejected under the same reasoning as claim 6 and claim 7. See both rejections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSH CHARLES GARDINER whose telephone number is (571)270-0634. The examiner can normally be reached 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Vladimir Magloire can be reached at (571) 270-5144. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSH CHARLES GARDINER/Examiner, Art Unit 3648
/VLADIMIR MAGLOIRE/Supervisory Patent Examiner, Art Unit 3648
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