Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 06/20/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The abstract of the disclosure is objected to because the abstract repeats information already present in the title. The abstract states “A memory cell group and a manufacturing method therefor are provided.”. The title already states “MEMORY CELL GROUP AND MANUFACTURING METHOD THEREFOR”. The abstract should be amended to remove the information already provided by the title. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6, 7, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140170830 A1 hereinafter Lee in further view of US 20190058007 A1 hereinafter Tsai.
For claim 1, Lee teaches a memory cell group (Lee, fig. 4) comprising: a first resistive memory cell (fig. 4 numeral MC2) comprising a first electrode (fig. 4 numeral 140), a first resistive layer (fig. 4 numeral 130), and a second electrode (fig. 4 numeral 10) and a second resistive memory cell (fig. 4 numeral MC1), wherein the second resistive memory cell comprises the second electrode (fig. 4 numeral 10), a second resistive layer (fig. 4 numeral 13), and a third electrode (fig. 4 numeral 14), wherein the first and second resistive memory cells share the second electrode (fig. 4 shows memory cells MC2 and MC1 sharing the second electrode 10). Lee also teaches the memory cells including a first line connected to the first electrode (fig. 5 numeral L1), a second line connected to the second electrode (fig. 5 numeral L2), and a third line connected to the third electrode (fig. 5 numeral L3). Lee is silent regarding the first line being connected to the first electrode through a first metal layer and the third line being connected to the third electrode through a second metal layer in order to achieve independent control over the first memory cell and the second memory cell respectively.
Tsai teaches a memory cell group (Tsai, fig. 2) including a first metal layer connected to a first line (fig. 2 numeral BL1) connecting the line to a first electrode (fig. 2 numeral LE1), and a second metal layer connected to a second line (fig. 2 numeral BL2) connecting the line to a third electrode (fig. 2 numeral UE2). Tsai does not explicitly state that the lines provide independent control over the first resistive memory cell and the second resistive memory cell. However, Tsai does state the lines allow for access to both memory cells, and the memory cells can be accessed separately and congruently to each other (fig. 1; Par. [0018]). Tsai also teaches a similar line connection scheme and configuration (fig. 1) as the immediate invention (immediate invention figure 3) wherein a singular word line (fig. 1 numeral WL) is connected to two bit lines (fig. 1 numeral BLT and BLC), the bit lines connected to the two resistive memory cells (fig. 1 numeral 102 and 104). As Tsai teaches all the limitations of the lines connected to metal layers and electrodes of the resistive memory cells, and teaches the control of both resistive memory cells (Par. [0018]); examiner is interpreting Tsai as teaching independent control over both the first resistive memory cell and the second resistive memory cell.
It would have bene obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the metal layers and line connections in Tsai with the shared electrode in Lee in order to have access to both resistive memory cells while maintaining a smaller device size (Tsai, Par. [0018]).
For claim 4, Lee and Tsai teach all of claim 1. Tsai also teaches the first line is a first bit line (Tsai, fig. 2 numeral BL1), and the third line is a second bit line (fig. 2 numeral BL2). The second line (fig. 2 numeral 204) connecting the two resistive memory cells (fig. 2 numeral 104 and 102) at the second electrodes (fig. 2 numeral LE2 and UE1) is a source line (Par. [0024]). Lee teaches the second electrode being connected to a line (Lee, fig. 5 numeral L2; Par. [0069]). It would have been obvious to one ordinary skill in the art before the effective filing date of the immediate invention to combine the source line and bit line connections in Tsai with the shared electrode in Lee in order to minimize the footprint of the device (Tsai, Par. [0018]) and achieve a fast write time (Tsai, Par. [0022]).
For claim 6, Lee and Tsai teach all of claim 1. Lee also teaches the memory group forming a three layer crossed array structure (Lee. fig. 5). Tsai teaches the first metal layer, the second metal layer, and the electrodes being in an array structure (Tsai, fig. 4) and in a stacked configuration (Tsai, fig. 2, fig. 5).
It would have been obvious to one of ordinary skill in the art to combine the three-layer crossed array structure in Lee with the array structure in Tsai in order to provide access to both resistive memory cells (Tsai, Par. [0092]) and to achieve greater switching characteristics through the three-layer crosses array structure (Lee, Par. [0072 - 0073]).
For claim 7, Lee teaches a manufacturing method for a memory cell group, comprising: forming a first resistive memory cell (Lee, fig. 4 numeral MC2), wherein the first resistive memory cell comprises a first electrode (fig. 4 numeral 140), a first resistive layer (fig. 4 numeral 130) and a second electrode (fig. 4 numeral 10); forming a second resistive memory cell on the second electrode (fig. 4 numeral MC1), wherein the second resistive memory cell comprises the second electrode (fig. 4 numeral 10), a second resistive layer (fig. 4 numeral 13) and a third electrode (fig. 4 numeral 14), wherein the second resistive memory cell and the first resistive memory cell share the second electrode (fig. 4 numeral 10). Lee also teaches performing a wiring for the memory cell group that includes first, second, and third line, wherein the first and second line are connected to the first resistive memory cell (fig. 5 numeral L1 and L2) and the second line and the third line are connected to the second resistive memory cell (fig. 5 numeral L2 and L3). Lee is silent regarding the first line being connected to the first electrode through a first metal layer comprising a substrate and the third line being connected to the third electrode through a second metal layer in order to achieve independent control over the first memory cell and the second memory cell respectively.
Tsai teaches forming two resistive memory cells (Tsai, fig. 2 numeral 104 and 102) comprising a substrate including a first metal layer wired to a first line (fig. 2 numeral BL1) on the first electrode (fig. 2 numeral LE1), wiring that includes a second metal layer wired to a third line (fig. 2 numeral BL2) and formed on a third electrode (fig. 2 numeral UE2), and wiring that includes a second line connected to the first resistive memory cell and the second memory cell (fig. 2 numeral 212). Tsai does not explicitly state that the lines provide independent control over the first resistive memory cell and the second resistive memory cell. However, Tsai does state the lines allow for access to both memory cells, and the memory cells can be accessed separately and congruently to each other (fig. 1; Par. [0018]). Tsai also teaches a similar line connection scheme and configuration (fig. 1) as the immediate invention (immediate invention figure 3) wherein a singular word line (fig. 1 numeral WL) is connected to two bit lines (fig. 1 numeral BLT and BLC), the bit lines connected to the two resistive memory cells (fig. 1 numeral 102 and 104). As Tsai teaches all the limitations of the lines connected to metal layers and electrodes of the resistive memory cells, and teaches the control of both resistive memory cells (Par. [0018]); examiner is interpreting Tsai as teaching independent control over both the first resistive memory cell and the second resistive memory cell.
It would have been obvious to one of ordinary skill in the art to before the effective filing date of the immediate invention to combine the wiring formation in Tsai with the shared electrode in Lee in order to have access to both resistive memory cells while maintaining a smaller device size (Tsai, Par. [0018]).
For claim 10, Lee and Tsai teach all of claim 7. . Lee also teaches the memory group forming a three layer crossed array structure (Lee. fig. 5). Tsai teaches the first metal layer, the second metal layer, and the electrodes being in an array structure (Tsai, fig. 4) and in a stacked configuration (Tsai, fig. 2, fig. 5).
It would have been obvious to one of ordinary skill in the art to combine the three-layer crossed array structure in Lee with the array structure in Tsai in order to provide access to both resistive memory cells (Tsai, Par. [0092]) and to achieve greater switching characteristics through the three-layer crosses array structure (Lee, Par. [0072 - 0073]).
Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140170830 A1 hereinafter Lee in view of US 20190058007 A1 hereinafter Tsai and in further view of US 20090134431 A1 hereinafter Tabata.
For claim 2, Lee and Tsai teach all of claim 1. Lee and Tsai are silent regarding the first resistive memory cell having a groove structure with an upward opening.
Tabata teaches a resistive memory cell, wherein the resistive memory cell have a groove structure with an upward opening (Tabata, fig. 3, fig. 14; fig. 22 numeral MA0 – MA3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the groove structure of Tabata with the shared electrode and metal layers in Lee and Tsai in order to suppress current leak (Tabata, Par. [0054]) and alleviate overheating (Tabata, Par. [0054]).
For claim 8, Lee and Tsai teach all of claim 7. Lee and Tsai are silent regarding the first resistive memory cell having a groove structure with an upward opening on a substrate.
Tabata teaches a resistive memory cell, wherein the resistive memory cell have a groove structure on a substrate with an upward opening (Tabata, fig. 3, fig. 14, fig. 16; fig. 22 numeral MA0 – MA3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the groove structure of Tabata with the shared electrode and metal layers in Lee and Tsai in order to suppress current leak (Tabata, Par. [0054]) and alleviate overheating (Tabata, Par. [0054]).
Claim(s) 3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140170830 A1 hereinafter Lee in view of US 20190058007 A1 hereinafter Tsai and in further view of US 20070246782 A1 hereinafter Philipp.
For claim 3 Lee and Tsai teach all of claim 1. Lee and Tsai are silent regarding the second resistive memory cell comprises a sidewall protective layer.
Philipp teaches a memory cell (Philipp, fig. 2) which includes a sidewall protection layer (fig. 2 numeral 126).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the sidewall protection layer in Philipp with the electrodes and metal layers in Lee and Tsai in order to improve the electrical properties of the resistive memory cell (Philipp, Par. [0053]) and protect the materials of the resistive memory cell during the formation process (Philipp, Par. [0068 – 0070]).
For claim 9, Lee and Tsai teach all of claim 7. Lee and Tsai are silent regarding the second resistive memory cell comprises a sidewall protective layer on the second electrode.
Philipp teaches the manufacturing of a memory cell (Phillip, fig. 9) that includes forming a sidewall protective layer (fig. 9 numeral 126) on a first and second electrode (fig. 9 numeral 120 and 122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the sidewall protection layer in Philipp with the electrodes and metal layers in Lee and Tsai in order to improve the electrical properties of the resistive memory cell (Philipp, Par. [0053]) and protect the materials of the resistive memory cell during the formation process (Philipp, Par. [0068 – 0070]).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 5, Lee, Tsai, Philipp, and Tabata do not appear to teach memory cell groups with multiple source lines, and wherein the multiple source lines are connected to the first and third electrodes with a first bit line connected to the second electrode that is shared between the resistive memory cells. Tsai appears to only teach configurations wherein bit lines are connected to the first and third electrodes, with a source line connected to a shared portion between resistive memory cells.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
Prosecution Insights