DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's submission filed on 05/18/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 9-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Andris et al. US 2022/0200467 A1 in a view of EPC, Optimizing PCB layout, 2019.
Regarding claim 20, Andris et al. disclose
A power tool [0026] comprising: a motor (fig. 1, item 114); a power source interface (item 112) configured to connect to a power source (Battery); and a printed circuit board ("PCB") (fig. 3, item 300) electrically connected to the motor and the power source interface (see fig. 1 for detail) [0030], wherein the PCB includes: wide band gap ("WBG") semiconductors [0029], a three-level or greater inverter (item 110) configured for controlling power supplied by the power source to the motor [0028, 0029], wherein a topology of the three-level or greater inverter is one of a flying capacitor multi- level ("FCML") inverter, a cascaded H-bridge inverter (semiconductor bridge), or a diode clamped inverter [0024,0025, 0031, 0034] (It should be noted that the inverter module is configured as a three-phase output).
Andris does not disclose but EPC discloses and wherein the PCB includes a first layer (top layer) and a second layer (bottom layer), a power loop where a first current flows on the PCB is configured to generate a first magnetic field (a magnetic field is generated because of current), a second current on the second layer of the PCB flows in the opposite direction of the first current, the second current generates a second magnetic field that is operable to counteract the first magnetic field.
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Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a first and second layer as disclosed by EPC in Andris teachings to reduce parasitic inductance.
Regarding claim 1, Andris et al. disclose
A power tool comprising: a motor; a power source interface configured to connect to a power source; and a printed circuit board ("PCB") electrically connected to the motor and the power source interface, the PCB including a three-level or greater inverter configured for controlling power supplied by the power source to the motor, wherein the PCB includes a first layer and a second layer, a power loop where a first current flows on the PCB is configured to generate a first magnetic field, a second current on the second layer of the PCB flows in the opposite direction of the first current, the second current generates a second magnetic field that is operable to counteract the first magnetic field. (see claim 20 rejection for detail).
Regarding claim 2, Andris and EPC discloses
the power loop is a lateral power loop; the second layer of the PCB is a shield layer of the PCB; the second layer is located in close proximity to the power loop; and the first current induces the second current on the second layer of the PCB (EPC’s teaches this).
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Regarding claim 4, Andris et al. disclose
, wherein the three-level or greater inverter is a three-level inverter, a five-level inverter, a seven-level inverter, a nine-level inverter, or an eleven-level inverter (It should be noted that the inverter module is configured as a three-phase output) [0029,0031].
Regarding claim 9, Andris et al. disclose
, wherein the PCB includes wide band gap ("WBG") semiconductors [0029].
Regarding claim 10, Andris et al. disclose
, wherein the WBG semiconductors include Gallium Nitride ("GaN") and/or Silicon Carbide ("SiC") [0029].
Regarding claim 11, EPC discloses
the power loop is a vertical power loop; the first layer is a top layer of the PCB; the second layer is a bottom layer of the PCB; and the first current flowing on the top layer is in an opposing direction to the second current flowing on the bottom layer
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Claims 3, 5-8 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Andris et al. in a view of EPC and further in a view of Christopher (“design and control….inverter) (IDS suppled NPL)
Regarding claim 3, a combination of Andris and EPC does not disclose but Christopher discloses wherein a switching frequency (effective switching frequency) of the three-level or greater inverter is a multiple (N-1) of a fundamental switching frequency (fsw) of the three-level or greater inverter, and a level of the three-level or greater inverter (N) is a multiplier of the fundamental switching frequency (fsw) (see section D. Inductor sizing section).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a switching frequency as a multiple and a level as a multiplier as disclosed by Christopher in Andris teachings to achieve high power density (Christopher’s abstract section)
Regarding claim 5, a combination of Andris and EPC does not disclose but Christopher discloses, wherein, during operation of the three-level or greater inverter, a modulation voltage between two levels is given by Vbus / (N-1), where N is a number of levels of the three-level or greater inverter (see section B. capacitance sizing).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a modulation voltage as disclosed by Christopher in Andris teachings to achieve high power density (Christopher’s abstract section)
Regarding claim 6, a combination of Andris and EPC does not disclose but Christopher discloses an inductor (fig. 1, item L) and a capacitor (Cout) at an output of the three-level or greater inverter (see fig. 1 for detail).
Regarding claim 7, a combination of Andris and EPC does not disclose but Christopher discloses, wherein a pulse frequency seen by the inductor is given by (N-1)fsm, where fsw is a switching frequency of at least one switch of the three-level or greater inverter (see section D. inductor Sizing).
Regarding claim 8, Andris, EPC and Christopher discloses, wherein an inductor ripple current of the three-level or greater inverter is defined according to ΔiL = 0.25VBus/ (N-1)2fswL, where L is the inductance of the inductor and VBUS is a bus voltage of the power tool (see section D inductor sizing) (Andris already discloses the power tool. Deff can be easily adjusted to 50% duty ratio to get 0.25. Fig. 6 shows Duty cycle reaches to 0.5 or 50%).
Regarding claim 14, Andris et al. disclose
A power tool [00025] comprising: a motor (fig. 1, item 114); a battery pack interface (item 112) configured to receive a battery pack (battery);
a printed circuit board (“PCB”) electrically connected to the motor and the battery pack interface (see fig. 1 for detail) [0030], the PCB including
a three-level or greater inverter (item 110) for controlling power supplied by the battery pack to the motor [0028, 0029],
Andris does not disclose but Christopher discloses wherein a switching frequency (effective switching frequency) of the three-level or greater inverter is a multiple (N-1) of a fundamental switching frequency (fsw) of the three-level or greater inverter, and a level of the three-level or greater inverter (N) is a multiplier of the fundamental switching frequency (see section D. Inductor sizing section), and
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a switching frequency as a multiple and a level as a multiplier as disclosed by Christopher in Andris teachings to achieve high power density (Christopher’s abstract section)
A combination of Andria and Christopher does not disclose but EPC discloses
the PCB includes a first layer (Top layer) and a second layer (bottom layer), a power loop where a first current flows on the PCB is configured to generate a first magnetic field (a magnetic field is generated because of current), a second current on the second layer of the PCB flows in the opposite direction of the first current, the second current generates a second magnetic field that is operable to counteract the first magnetic field.
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Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a first and second layer as disclosed by EPC in Andris teachings to reduce parasitic inductance.
Regarding claim 15, Andris et a. disclose
, wherein the three-level or greater inverter is a three-level inverter, a five-level inverter, a seven-level inverter, a nine-level inverter, or an eleven-level inverter (see claim 4 rejection for detail).
Regarding claim 16, Andris et al. disclose
wherein, during operation of the three-level or greater inverter, a modulation voltage between two levels is given by Vbus / (N-1), where N is a number of levels (see claim 5 rejection for detail).
Regarding claim 17, Andris et al. disclose
: an inductor and a capacitor at an output of the three-level or greater inverter, wherein a pulse frequency seen by the inductor is given by (N-1)fsm, where fsw is a switching frequency of at least one switch of the three-level or greater inverter (see claim 7 rejection for detail).
Regarding claim 18, Andris et al. disclose
, wherein an inductor ripple current of the three-level or greater inverter is defined according to AiL = 0.25VBus/ (N-1)2fswL, where L is the inductance of the inductor and VBUSis a bus voltage of the power tool (see claim 8 rejection for detail).
Regarding claim 19, Andris et al. disclose
, wherein the three-level or greater inverter is a cascaded H- bridge inverter or a diode clamped inverter (see claim 11 rejection for detail).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Andris et al. in a view of EPC and further in a view of White et al. US Pub. No. 2016/0020443 A1
Regarding claim 12, a combination of Andris and EPC does not disclose but White et al. disclose wherein the battery pack has a nominal voltage of greater than 50V DC [0485].
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a nominal battery voltage of greater than 50V DC as disclosed by White in Andris’s teachings to operate the power tool using broader operating range (White’s paragraph 0485)
Regarding claim 13, EPC discloses the power loop is an optimized power loop (Vertical power loop); the second layer is a first inner layer of the PCB and is used as a power loop return path; and the return path is located directly beneath the first layer.
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Response to Arguments
Applicant’s arguments with respect to claims 1, 14 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see updated claim rejection for details).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BICKEY DHAKAL whose telephone number is (571)272-3577. The examiner can normally be reached 8:30-4:30 PM.
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/BICKEY DHAKAL/Primary Examiner, Art Unit 2837
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