Prosecution Insights
Last updated: April 19, 2026
Application No. 18/717,452

Method for Operating a Circuit Arrangement and Circuit Arrangement

Final Rejection §102
Filed
Jun 07, 2024
Examiner
LAM, TUAN THIEU
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
AMS-OSRAM AG
OA Round
2 (Final)
77%
Grant Probability
Favorable
3-4
OA Rounds
2y 1m
To Grant
91%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
775 granted / 1001 resolved
+9.4% vs TC avg
Moderate +13% lift
Without
With
+13.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
34 currently pending
Career history
1035
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
36.8%
-3.2% vs TC avg
§102
36.3%
-3.7% vs TC avg
§112
20.0%
-20.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1001 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a response to the amendment filed 12/23/2025. Claims 1-4 and 7-15 are pending and are under examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Proksa et al. (US 2010/027472). Regarding claims 1 and 12, Proska et al.’s figure 5A shows a method for operating a circuit arrangement, the method comprising: receiving an input voltage signal (Pulse shaper) with an input voltage level by at least one first comparator (comparator 1) and by at least one second comparator (comparator 2), comparing the input voltage level to a first voltage level (Th1) by the first comparator; comparing the input voltage level to a second voltage level (Th2) by the second comparator; incrementing a first counter (one counter 236 per threshold voltage; see paragraph 0025) assigned to the first comparator once the input voltage level is higher than the first voltage level (figure 1, CNT1); incrementing the first counter again after the input voltage level being lower and higher again than the first voltage level (figure 6, 628); incrementing a second counter (sub counter 236 for a second threshold voltage) assigned to the second comparator once the input voltage level is higher than the second voltage level (CNT2, 608, figure 6); incrementing the second counter again after the input voltage level being lower and higher again than the second voltage level (CNT2, 628; figure 6); and incrementing the first counter by at least 1 again once the second counter was incremented twice without the first counter being incremented in between (CNT1, 628; figure 6, rising 316), wherein the absolute value of the first voltage level (Th1) is lower than the absolute value of the second voltage (Th2); wherein the input voltage signal is received by a pile-up comparator (comparator N), the pile-up comparator compares the input voltage level to a pile-up voltage level (THN) 608, thus, the limitations of “wherein the first counter (first subcounter 236) and the second counter (second subcounter 236) are both incremented by at least 1 once the input voltage level is higher than the pile-up voltage level” is met) as called for in claims 1 and 12. Regarding claim 2; wherein the first counter (first subcounter 236) Regarding claim 3, wherein the input voltage signal is provided by a frontend circuit (220; figure 2) of a photon counting system, and the frontend circuit is configured to convert current pulses generated by a photon detector into voltage pulses forming the input voltage signal. Regarding claim 4, wherein the first counter (first subcounter 236) is incremented by 1 once the input voltage level is higher than the first voltage level (CNT1, figure 6) and the second counter (second subcounter 236, CNT2, figure 6) is incremented by 1 once the input voltage level is higher than the second voltage level. Regarding claim 13, the first counter is connected to the second counter to form a multiple subcounter 236. Regarding claim 14, wherein the circuit arrangement comprises a pile-up comparator (comparator N) that is connected with the input and that is configured to compare the input voltage level to a pile-up voltage level (THN), the absolute value of the pile-up voltage level (THN) is higher than the absolute value of the first voltage level (TH1) and the absolute value of the second voltage level (TH2), and the first counter (first subcounter 236) and the second counter (second subcounter 236) formed the counter 236 that is connected with the pile-up comparator via a subcounter N. Response to Arguments Applicant's arguments filed 12/23/2025 have been fully considered but they are not persuasive. Applicant argues that Proksa et al. reference fails to teach “wherein the first counter and the second counter are both incremented by at least 1 once the input voltage level is higher than the pile-up voltage level” as called for in claims 1 and 12 found not persuasive. Since Proksa et al.’s pile-up voltage (TH6) is higher than both the first and second voltage levels (TH6 is larger than TH1 and TH2) and by the time the input voltage level is higher than the pile up voltage at 644, both the first and second counter have already incremented by one at 604 and 608, thus, the limitations of “wherein the first counter (first subcounter 236) and the second counter (second subcounter 236) are both incremented by at least 1 once the input voltage level is higher than the pile-up voltage level” is met. The rejection is deemed proper. Claims 1-4, 12-14 remain rejected. Allowable Subject Matter Claims 7-10 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 11 is presently allowed. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T LAM/Primary Examiner, Art Unit 2842 2/14/2026
Read full office action

Prosecution Timeline

Jun 07, 2024
Application Filed
Oct 03, 2025
Non-Final Rejection — §102
Dec 23, 2025
Response Filed
Feb 20, 2026
Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
77%
Grant Probability
91%
With Interview (+13.3%)
2y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 1001 resolved cases by this examiner. Grant probability derived from career allow rate.

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