Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This is the initial Office Action based on the application filed on June 07, 2024. The Examiner acknowledges the following:
3. Claims 1 – 16 were filed by Applicant.
4. The specification was amended as to includes the Cross-reference related application.
5. The drawings filed on 06/07/2024are accepted by the Examiner.
6. Current claims 1 – 16 are pending and they are being considered for examination.
Information Disclosure Statement
7. The IDS document filed on filed on 06/07/2024 is acknowledged by the Examiner.
Priority
8. Priority data is based on a PCT application PCT/JP2022/044873, filed on 12/06/2022, which refers to a prior Japanese patent application JP-2021-203484 filed on 12/15/2021. Certified copies were filed to the office on06/07/2024.
Claim Interpretation under 112(f)
9. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
1. Use of the word “means” (or “step for”) in a claim with functional language creates a rebuttable presumption that the claim element is to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is invoked is rebutted when the function is recited with sufficient structure, material, or acts within the claim itself to entirely perform the recited function.
2. Absence of the word “means” (or “step for”) in a claim creates a rebuttable presumption that the claim element is not to be treated in accordance with 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph). The presumption that 35 U.S.C. 112(f) (pre-AIA 35 U.S.C. 112, sixth paragraph) is not invoked is rebutted when the claim element recites function but fails to recite sufficiently definite structure, material or acts to perform that function.
3. Claim elements in this application that use the word “means” (or “step for”) are presumed to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Similarly, claim elements that do not use the word “means” (or “step for”) are presumed not to invoke 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
7. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification, as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
8. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “a first photoelectric conversion section”, “a second photoelectric conversion section”.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Yusuke Kohyama, WO-2021-124974 (A1), hereinafter Kohyama”. (Note: Kohyama art is from the IDS document – The translation is provided by the Examiner.)
Regarding Claims 1 – 5 and 16:
Kohyama teaches an imaging device with a semiconductor substrate having a plurality of sensor pixels for performing photoelectric conversion arrayed in a matrix, and a circuit layer including a plurality of pixel circuits that output pixel signals on the basis of charges output from each of the sensor pixels, the circuit layer being disposed on the semiconductor substrate with an interlayer dielectric layer therebetween. A gate electrode of at least one transistor included in the pixel circuits extends across the plurality of pixel circuits in the plane of the circuit layer, and electrically connects to the gate electrode of the same type of the transistor provided in each of the plurality of the pixel circuits.
A solid-state imaging device (Fig 1, imaging device 1. See [0037]) comprising: a first photoelectric conversion section that generates an electric charge corresponding to an incident light amount (Fig 1, Figs. 4A, 4B shows a semiconductor substrate with includes a plurality of pixels and pixel circuits including a pixel 12 with a photodiode PD. See [0014;0018; 0033; 0040; 0048; 0051]); a second photoelectric conversion section that is adjacent to the first photoelectric conversion section and generates an electric charge corresponding to an incident light amount (Fig 1, Figs. 4A, 4B shows a semiconductor substrate with includes a plurality of pixels and pixel circuits including another pixel 12 adjacent to the first pixel 12with a photodiode PD. See [0014;0018; 0033; 0040; 0048; 0051]);
a floating diffusion region that accumulates the electric charge generated in at least one of the first photoelectric conversion section (Fig 1, Figs 4A, 4B, a n-type floating diffusion region FD, which is shared by 4 (four) sensor pixels 12. See [0018; 0028; 0044; 0047]) and the second photoelectric conversion section (the FD is shared by 4 (four) photodiodes PD);
a first transfer transistor connected between the first photoelectric conversion section and the floating diffusion region; a second transfer transistor connected between the second photoelectric conversion section and the floating diffusion region (Fis 1, 4A, 4B, transfer transistor TR. With a vertical gate electrode TG1 for a first photodiode and TG2 for a second photodiode PD See [0018; 0027; 0049]);
a first drive line connected to a gate of the first transfer transistor; and a second drive line connected to a gate of the second transfer transistor (Figs 2, 3pixel drive lines. See [0027; 0032; 0038]),
wherein coupling capacitance between the second drive line and the floating diffusion region is smaller than coupling capacitance between the first drive line and the floating diffusion region (Fig 4A,the facing area and distance between the wiring layer 611 and the floating diffusion region FD (and contact plug 620) are different form the facing area and distance between the wiring layer 612 and the floating diffusion region FD (and contact plug 620) and the respective coupling capacitance are understood as being different (See [0029; 0030; 0031; 0039]). Additionally, Kohyama teaches that Wiring layers 611, 612, 613, and 614 that are routed up to above the element isolation portion 43 are provided on the vertical gate electrodes TG1, TG2, TG3, and TG4 via an insulating layer 46A. Contact plugs 621 , 622 , 623 , and 624 that penetrate the circuit insulating layer 47 are provided in the wiring layers 611 , 612 , 613 , and 614 on the element isolation portion 43 at a later stage (See [0049]).
As for the limitations:
Metal wires/ wiring layers 611,612,613 and 614 (See [0049]).
Interlayer insulating film/material is formed on the semiconductor layer 48 (See [0006; 0007; 0055]).
As for claim 16: Fig 18 shows imaging system 900 or image device as a camera or electronic device, including imaging device 1, a digital signal processor DSP 943 for processing the images output by imaging device 1, a frame memory 944, a display 945, a memory unit 946, an operation unit 947 and a power supply 948 (See [0093- 0095])..
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Keiji Mabuchi et al., JP-2010-278795 (A), hereinafter Mabuchi”. (Note: Mabuchi art is from the IDS document – The translation is provided by the Examiner.)
Regarding Claim 12:
Mabuchi teaches a solid-state device including a photoelectric conversion unit; and a transfer gate unit that transfers charges photoelectrically converted by the photoelectric conversion unit to the charge voltage conversion unit, and charges overflowing from the photoelectric conversion unit are transferred to the charge voltage conversion unit through the transfer gate unit. Pixels having a structure to be discarded are arranged in a matrix, and at least the pixel array unit sharing the charge-voltage conversion unit among a plurality of pixels. A pixel that shares the charge-voltage converter with the pixels in the readout row simultaneously with or prior to reading the signals from the pixels in the readout row while scanning the row from which the signals are read out from each pixel of the pixel array unit A solid-state imaging device comprising: a row scanning unit that resets charges in the photoelectric conversion unit, wherein the pixel has a back-illuminated pixel structure that takes in incident light from a side opposite to a side where a wiring layer is disposed with respect to the photoelectric conversion unit.
As for claim 12 limitations, Mabuchi teaches,
A solid-state imaging device (Fig 1 shows the system configuration of an imaging device with a CMOS image sensor 10 with pixel array 12 with pixels in a matrix. See [0018 – 0028]) comprising: a first photoelectric conversion section that generates an electric charge corresponding to an incident light amount (Fig 4, photodiode 31-1. See [0047]]); a second photoelectric conversion section that is adjacent to the first photoelectric conversion section and generates an electric charge corresponding to an incident light amount (Fig 4, photodiode 31-2. See [0047]);
a floating diffusion region that accumulates the electric charge generated in at least one of the first photoelectric conversion section and the second photoelectric conversion section (Fig 4, floating diffusion section 35 with FD1 shared by photodiodes 31-1 and 31-2. See [0046; 0047]);
a first transfer transistor connected between the first photoelectric conversion section and the floating diffusion region (Fig 4, transfer transistor 32-1 of pixel 30-1, connected between the photodiode 31-1 and the floating diffusion FD1. See [0052]); a second transfer transistor connected between the second photoelectric conversion section and the floating diffusion region (Fig 4, transfer transistor 32-1 between the photodiode 31-2 and the floating diffusion FD1. See [0054]);
a first drive line connected to a gate of the first transfer transistor (Fig 1, pixel drive line 17 is connected to the gate electrode of the transfer transistor 32-1 and to which the transfer pulse TRG1 is applied. See [0021]); a second drive line connected to a gate of the second transfer transistor Fig 1, another pixel drive line 17 is connected to the gate electrode of the transfer transistor 32-2 and to which the pulse transfer is applied); and
a drive circuit that applies a drive signal to each of the first drive line and the second drive line (Fig 1, row scanning section/vertical driving section 13, which provides the drive signal for each of the pixel drive line 17. See [0019; 0021; 0022; 0041; 0042]), wherein
the first photoelectric conversion section (Fig 4, photodiode 31-1), the first transfer transistor (Fig 4, transfer 32-1), and the floating diffusion region configure a first pixel (Fig 4, FD1); which form pixel 30-1. See [0046; 0047]), the second photoelectric conversion section (Fig 4, photodiode 31-2), the second transfer transistor (Fig 4, transfer 32-2), and the floating diffusion region (Fig 4, FD1), which form pixel 30-2) configure a second pixel, and
the drive circuit (Fig 1, drive section 13 which applies the drive signals to the pixel drive line 17) applies a first drive signal to the first drive line at a time of read from the first pixel and applies a third drive signal to the second drive line after applying a second drive signal to the first drive line at a time of read from the second pixel (Fig 5, timing chart for the solid-state imaging device operation the transfer pulse TRG1 is applied and then, at time t25, the transfer pulse TRG2 is applied and the signal charge is photoelectrically converted in the pixel 30-2 is transferred. See [0057; 0064]).
Claims 13 – 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Sohei Manabe et. Al., US 2015/0172579 A1”. (Note; this art is from the IDS document).
Regarding Claims 13 – 15:
Manabe teaches apparatus and method, which includes an image sensor with photosensitive regions, transfer transistors, and one or more shared charge-to-voltage mechanism and wherein it teaches a method for reading out the image sensor that includes enabling a first transfer transistor to transfer photo-generated charge from a first photosensitive region to a shared charge-to-voltage mechanism. The method also includes no more than partially enabling a second transfer transistor to partially turn on the second transfer transistor to increase a capacitance of the shared charge-to-voltage mechanism while the photo-generated charge is transferred from the first photosensitive region to the shared charge-to-voltage mechanism.
As for claims 13 – 15 limitations, Manabe teaches,
A solid-state imaging device (Fig 1, imaging device/system 100 with pixel array 102, with a plurality of pixel cells Pi. See [0018 – 0020]) comprising: a first photoelectric conversion section that generates an electric charge corresponding to an incident light amount (Fig 2A, first photodiode PD1. See [0021; 0024]); a second photoelectric conversion section (Fig 2A, photodiode PD2. See [0021; 0024]) that is adjacent to the first photoelectric conversion section and generates an electric charge corresponding to an incident light amount;
a floating diffusion region that accumulates the electric charge generated in at least one of the first photoelectric conversion section and the second photoelectric conversion section (Fig 2A, floating diffusion FD 230 is shared by two photodiodes PD1 and PD2. See [0023]);
a first transfer transistor connected between the first photoelectric conversion section and the floating diffusion region (Fig 2A, transfer transistor 220 connected between the photodiode PD1 and the floating diffusion 230. See [0022]); a second transfer transistor connected between the second photoelectric conversion section and the floating diffusion region (Fig 2A, transfer transistor 225 connected between the photodiode PD2 and the floating diffusion 230. See [0022]);
a first drive line connected to a gate of the first transfer transistor (Fig 2A, 2B, a first transfer TX1signal with connection/wire that is connected to the gate terminal of the first transfer transistor 220. See [0022]); a second drive line connected to a gate of the second transfer transistor (Fig 2A, 2B, a second transfer TX2 signal with connection/wire that is connected to the gate terminal of the first transfer transistor 220. See [0022],); and
a drive circuit that applies a drive signal to each of the first drive line and the second drive line (Fig 1, control circuit 138 corresponds to the drive circuit, which drives the signal to the pixel rows/columns of the pixel array 102. See [0018]), wherein
the first photoelectric conversion section, the first transfer transistor, and the floating diffusion region configure a first pixel (Fig 2A , PD1, transfer transistor 220 and floating diffusion region 230 form the first pixel) the second photoelectric conversion section, the second transfer transistor, and the floating diffusion region configure a second pixel (Fig 2A , PD2, transfer transistor 225 and floating diffusion region 230 form the second pixel),
the drive circuit (Fig 1, control circuit 138 corresponds to the drive circuit, which drives the signal to the pixel rows/columns of the pixel array 102. See [0018]) applies a first drive signal to the first drive line at a time of read from the first pixel and applies a second drive signal to the first drive line and applies a third drive signal to the second drive line at a time of read from the second pixel, and a voltage level of at least one of the second drive signal and the third drive signal is lower than a voltage level of the first drive signal (Fig 2A, 2B, the charges generated by PD1 is transferred to the floating diffusion region 230 via transfer signal TX1 during the first transfer period, the signal TX is asserted by applying an enabling voltage Ven to the gate terminal of the first transfer transistor 220. At the same time, the charges generated by PD2 are transferred to the floating diffusion region 230, by applying a boost transfer voltage Vtxm is applied to the terminal of the second transfer transistor 225 to partially enable (partially turn it ON) the second transfer transistor 225. The boost voltage Vtxm is less that the threshold/enable voltage See [0025; 0028; 0029]).
Claim Objections – Allowable Subject Matter
11. claims 6 – 11 are objected as being dependent to a rejected claim. However, they would be allowable if written into independent form.
Contact
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARLY CAMARGO whose telephone number is (571)270-3729. The examiner can normally be reached on 6:00AM - 10PM, M-F, EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached on (571)272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARLY S CAMARGO/Primary Examiner, Art Unit 2638