DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first dipole being a resistor, as recited in claim 1, in combination with the first dipole being “an enhancement-mode transistor, the gate of which is connected to its drain”, as recited in claim 7, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The amendment filed 10/22/25 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
With respect to claim 7, the recitation of “the first dipole is an enhancement-mode transistor, the gate of which is connected to its drain” in combination with the first dipole being a resistor as recited in claim 1 is not supported by the original disclosure.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 7 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
With respect to claim 7, the recitation of “the first dipole is an enhancement-mode transistor, the gate of which is connected to its drain” in combination with the first dipole being a resistor as recited in claim 1 is not supported by the original disclosure.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 7, “the first dipole is an enhancement-mode transistor, the gate of which is connected to its drain” in combination with the first dipole being a resistor as recited in claim 1 cannot be understood, since it is not supported by the original disclosure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iriarte et al. (USPN 9,632,521).
Examiner’s Markup of Iriarte et al.
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With respect to claim 1, Iriarte et al. discloses, in Figs. 3, 15 and 18, a voltage reference circuit (the circuit of Fig. 3, wherein the circuit of Fig. 15 replaces the circuit of 60 of Fig. 3, see Col. 3 lines 55-57 and Col. 16 lines 27-34, and wherein the circuit of Fig. 18 replaces 42 of 40 of Fig. 3, see Col. 16 line 62 to Col. 17 line 2. See also combined circuit in Examiner’s Markup of Iriarte, “markup” hereinafter) comprising:
- a leading depletion-mode transistor (42-1 of Fig. 18), a drain of which is connected to a voltage source (e.g., 30 see the markup),
- a trailing depletion-mode transistor (42-4 of Fig. 18, wherein Fig. 18 is used in place of 40 of Fig. 3, see the markup), a source of which is connected to a terminal of a first dipole (source connected to a terminal of dipole R1), and a gate of which is connected to a second terminal of the first dipole (gate of 42-4 connected to the other terminal of dipole R1),
- a connecting quadrupole (42-2 with 42-3 of Fig. 18), a first terminal of which is connected to the gate of the leading transistor (see gate terminal of 42-1 and Q1 of the markup), a second terminal of which is connected to the source of the leading transistor (see drain of 42-2 and Q2 of the markup), a third terminal of which is connected to the source of the trailing transistor (see gate of 42-3 and Q3 of the markup) and a fourth terminal of which is connected to the drain of the trailing transistor (see source terminal of 42-3 and Q2 of the markup), the reference voltage being supplied to the source of the leading transistor (4*(VGSN) voltage at the source of 42-1 of Fig. 18),
- a base enhancement-mode transistor (one of 62-1 to 62-4 of Fig. 15 when used as 60 of Fig. 3, e.g., 62-4, see the markup), the source of which is connected to a ground (sources connected to 0V either directly or via at least one other 62-2 to 6-4, see the markup), and the gate of which is connected to its drain (gate and drains of each of 62-1 to 62-4 are connected), said drain being connected to a second terminal of a second dipole (either directly or via at least one of 62-3 to 62-1, the “second dipole” being a short circuit between the resistor and 62-1. Applicant suggests the dipole being a short, see claim 8. Furthermore, the second dipole may be at least another one of 62-1 to 62-4 that is not the “base enhancement-mode” transistor), the first terminal of which is connected to the second terminal of the first dipole (the first terminal of the above dipoles are connected to the second terminal of R1),
wherein the first dipole is a resistor (R1 is a resistor), and
the transistors are N-channel (the transistors are N-channel devices).
Iriarte et al. explicitly shows in the combination of the circuitry of Figs. 15 and 18 that there are an equal number of depletion-mode transistors and enhancement mode transistors (i.e., four of each).
Thus, Iriarte et al. fails to explicitly show, in the combined circuitry of Figs. 15 and 18, that “the circuit comprises exactly twice as many depletion-mode transistors as enhancement-mode transistors”.
Nevertheless, Iriate et al. suggests that there may be an arbitrary amount (i.e., “N”) transistors of 62-1 to 62-4 of Fig. 15 for the purpose of providing a desired voltage drop level and thus a desired output voltage value (see Col. 16 lines 30-32: “N transistor connected in series would give a voltage drop of NVgs2(I), in which N is a positive integer”) and/or temperature characteristics of the output voltage (see Fig. 2 and Col. 6 line 58 to Col. 7 line 12). It is further noted that the amount of transistors within the circuit of Fig. 18 is suggested by Iriate et al. to be selected to any given amount to provide a desired output voltage level (see Col. 16 line 62 to Col. 17 line 2).
It would have been obvious to select the amount of transistors within Fig. 15 of Iriate et al. such that the circuit comprises exactly twice as many depletion-mode transistors as enhancement-mode transistors (e.g., set N to equal two of Fig. 15 when Fig. 18 includes 4 transistors, or any other combination of transistors such that the amount of transistors of Fig. 18 is twice the amount of transistors of Fig. 15), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to set the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
It is further noted removal/omission of elements is known in the art since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. Moreover, the duplication of elements is also known, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore it would have been obvious to add and/or remove any desired number of the transistors of Figs. 15 and Fig. 18 within the circuit of Fig. 3 for the purpose of setting the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
Assuming, arguendo, that the transistors of Figs. 3 and/or 18 are “native transistors” and not explicitly disclosed as depletion-mode transistors. It is old and well-known to replace native transistors in a reference voltage generating circuit connected as shown in Iriarte et al. with depletion-mode transistors as evidenced in Col. 7 line 66 to Col. 8 line 2. As can be seen Iriarte discloses that native transistors and depletion mode transistors are art recognized equivalents and depletion mode transistors may be used in place of native transistors. It would have been obvious to replace the native transistors with depletion mode transistors, as suggested by Iriarte et al., since they are art recognized equivalents as evidenced by Iriarte et al. One would have been motivated to do so based on the types of transistors available at the time of construction of the circuit.
With respect to claim 2, Iriarte et al. fails to explicitly disclose, in Fig. 18, “that the connecting quadrupole consists of two short-circuits respectively connecting the first and third terminals and the second and fourth terminals”. However, the circuit will be connected and operative as claimed when it is desired to have transistors of Fig. 18 to have a contribution of -2Vgs1(I), instead of -4Vgs(I) of Col. 16 line 62 to Col. 17 line 2 (i.e., Fig. 18 including only 2 transistors) and the voltage drop of Fig. 15 to have only a single diode voltage drop (e.g., the circuit of 60 as shown in Fig. 3). It would have been obvious to construct the circuits of Figs. 3, 15 and 16 such that 60 includes a single transistor and 42 of Fig. 18 includes only two transistors (i.e., the quadrupole is shorted), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to set the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
It is further noted removal/omission of elements is known in the art since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. Moreover, the duplication of elements is also known, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore it would have been obvious to add and/or remove any desired number of the transistors of Figs. 15 and Fig. 18 within the circuit of Fig. 3 for the purpose of setting the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
With respect to claim 3, a voltage reference circuit according to claim 1, characterized in that the connecting quadrupole comprises two depletion-mode transistors (e.g., 42-2 and 42-3 of Fig. 18):
a top transistor (42-2) and a bottom transistor (42-3), the source of the top transistor being connected to the drain of the bottom transistor (source and drains connected as claimed) and to the first terminal of the connecting quadrupole (gate of 42-1/Q1 of the markup), the drain of the top transistor being connected to the second terminal of the connecting quadrupole (drain of 42-2/Q2 of the markup), the gate of the bottom transistor being connected to the third terminal of the connecting quadrupole (gate of 42-3/Q3 of the markup), and the gate of the top transistor and the source of the bottom transistor being connected to the fourth terminal of the connecting quadrupole (gate of 42-2/Q4 of the markup).
With respect to claim 4, a voltage reference circuit according to claim 1 characterized in that the connecting quadrupole consists of an elementary quadrupoles, with n = 1, each elementary quadrupole comprising two depletion-mode transistors (e.g., 42-2 with 42-3 of Fig. 18):
a top transistor (42-2) and a bottom transistor (42-3), the source of the top transistor being connected to the drain of the bottom transistor (source and drain connected as recited) and to a first terminal of the elementary quadrupole (gate of 421/Q1 of the markup), the drain of the top transistor being connected to a second terminal of the elementary quadrupole (drain of 42-2/Q2 of the markup), the gate of the bottom transistor being connected to a third terminal of the elementary quadrupole (gate of 42-3/Q3 of the markup), and the gate of the top transistor and the source of the bottom transistor being connected to a fourth terminal of the elementary quadrupole (gate of 42-2/source of 42-3/Q4 of the markup);
the third and the fourth terminals of the last elementary quadrupole forming the third and the fourth terminals of the connecting quadrupole (third and fourth terminals of the last quadrupole are the connecting, i.e., the first is the last when n=1).
Iriarte et al. fails to explicitly disclose “the elementary quadrupoles being connected in series, with two consecutive elementary quadrupoles connected such that the first terminal of one elementary quadrupole is connected to the third terminal of the preceding elementary quadrupole and the second terminal of said one elementary quadrupole is connected to the fourth terminal of the preceding elementary quadrupole; and the first and the second terminals of the first elementary quadrupole forming the first and the second terminals of the connecting quadrupole, and
the third and the fourth terminals of the last elementary quadrupole forming the third and the fourth terminals of the connecting quadrupole”.
However, the circuit will be connected as claimed when it is desired to generate a voltage the circuit will be connected and operative as claimed when it is desired to have transistors of Fig. 18 to have a contribution of -nVgs1(I), when “n” is any even value larger than four, instead of -4Vgs(I) of Col. 16 line 62 to Col. 17 line 2 (i.e., Fig. 18 including an even number of transistors above four) and the voltage drop of Fig. 15 to has a value that is equal to n/2. It would have been obvious to construct the circuits of Figs. 3, 15 and 16 such that 42 of Fig. 18 includes an even number greater than four and Fig. 15 includes a number of transistors that is half the amount of the transistors of Fig. 18, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to set the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
It is further noted removal/omission of elements is known in the art since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. Moreover, the duplication of elements is also known, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore it would have been obvious to add and/or remove any desired number of the transistors of Figs. 15 and Fig. 18 within the circuit of Fig. 3 for the purpose of setting the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
With respect to claim 5, a voltage reference circuit according to claim 1,characterized in that the depletion-mode and enhancement-mode transistors are GaN transistors or MOS transistors (the transistors are NMOS transistors, see Col. 1 line 66 to Col. 2 line 2).
With respect to claim 7, as far as can be understood, a voltage reference circuit according to claim 1, characterized in that the first dipole is an enhancement-mode transistor, the gate of which is connected to its drain (Fig. 15 includes additional diode connected voltage dropping transistors which may be interpreted as a first dipole circuit operative with resistor R1).
With respect to claim 8, a voltage reference circuit according to claim 2, characterized in that the second dipole is a short-circuit (the second dipole may be interpreted as the short circuit as discussed above).
With respect to claim 9, a voltage reference circuit according to claim 3,characterised characterized in that the second dipole comprises an enhancement-mode transistor, the source of which is connected to the second terminal of the second dipole and the gate of which is connected to its drain, said drain being connected to the first terminal of the second dipole (at least one of the two transistors of Fig. 15 is the second dipole connected and operative as claimed when there are only four transistors within the circuit of Fig. 18 and there are only two transistors within the circuit of Fig. 15 as modified above with respect to claim 3).
With respect to claim 10, a voltage reference circuit according to claim 4, characterized in that the second dipole comprises n enhancement-mode transistors, each of said transistors having its gate connected to its drain, said transistors being connected in series, two consecutive transistors being connected by the source of one and the drain of the other, the drain of the first transistor forming the first terminal of the second dipole and the source of the last transistor forming the second terminal of the second dipole (the n/2 transistors of Fig. 15 will be connected as claimed when it is desired to have transistors of Fig. 18 to have a contribution of -nVgs1(I), when “n” is any even value larger than four, instead of -4Vgs(I) of Col. 16 line 62 to Col. 17 line 2, i.e., Fig. 18 including an even number of transistors above four, and the voltage drop of Fig. 15 to has a value that is equal to n/2 as discussed above with respect to the rejection of claim 4).
Response to Arguments
Applicant's arguments filed 10/22/25 have been fully considered but they are not persuasive.
With respect to rejections under Iriarte et al. Applicant does not address the rejections with respect to Figs. 15 and 18, since the above rejection was not previously discussed with respect to the circuitry as disclosed in Figs. 15 and 18. Thus, Applicant’s arguments with respect to Iriarte et al. are moot. Nevertheless, Applicant argues that “[t]here is no teaching or suggestion in the cited references to use depletion-type transistors for the leading and trailing transistors and an enhancement-type transistor for the base transistor, while maintaining the claimed 2:1 ratio and all N-channel” is not persuasive. Iriarte does not explicitly disclose the ratio of 2:1 since Fig. 15 explicitly discloses the inclusion of four transistors (i.e., N=4). However, Iriarte suggests that N may be any desired value to set a desired voltage drop of the circuit of since stage “[m]ultiple transistors” within stage 60 of Fig. 15 “may be provided” and “N transistors connected in series would give a voltage drop of NVgs2(I) in which N is a positive integer”. Thus, Iriarte implicitly states that there may be only two transistor if N is equal to two. Furthermore, Iriarte provides the effective result of selecting a desired value of N in that it sets the voltage drop that to a specific/desired value. Thus, providing motivation for adjusting the amount of transistors within the circuit of Fig. 15. Therefore Applicant’s arguments are not persuasive.
The arguments that “[t]he use of a resistor as the first dipole is not a mere substitution for a transistor” and as “explained in the specification (page 11, lines 3-5), the resistor specifically reduces the impact of process variation on the reference voltage by a factor of 10, an effect not achieved by the active device in Lai” are not persuasive. This is because Iriarte explicitly discloses a resistor as the first dipole. Furthermore, the claims are not rejected under Lai and such a point is moot.
The argument that the “precise 2:1 ratio of N-channel depletion to enhancement transistors is not arbitrary, but is critical for threshold voltage compensation and process insensitivity” is not persuasive. This is because while Applicant may have different reasons for providing such a ratio, Iriarte implicitly suggest such a ratio is capable of being provides when N, of the circuit of Fig. 15 used in the circuit of Fig. 3, is equal to two and the circuit of Fig. 18 uses the four shown transistors of Fig. 18 in circuit of Fig. 3.
With respect to the Graham factor argument that “Lia nor Iriarte teaches or suggest the claimed configuration”. The above argument is false since Iriarte implicitly suggests such a configuration when N is equal to two. The Graham factor argument of “the prior art lacks the specific combination of a resistor being a first dipole, 2:1 depletion-mode transistor: enhancement- mode transistor ratio, all transistors being N-channel, and the specific transistor staging” is not persuasive, since Irate suggests such a construction as discussed above. The argument that the “skilled artisan would not be motivated to combine the cited elements in the claimed manner, nor would there be a reasonable expectation of achieving the observed process insensitivity and low current consumption” is not persuasive, since Iriarte et al. implicitly suggest that the circuit is capable of being operated as claimed when N equals two. The argument that the ”improved stability and process robustness are unexpected results not suggested by the prior art” is not persuasive, since when N is equal to two the circuit will be connected as claimed and thus provides for such functionality.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849
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