DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Iriarte et al. (USPN 9,632,521).
Markup1: Examiner’s Markup of the combination of Figs. 15 and 18 Iriarte et al.
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Markup2: Examiner’s Markup of the modified combination of Figs. 15 and 18 Iriarte et al.
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With respect to claim 1, Iriarte et al. discloses, in Figs. 3, 15 and 18, a voltage reference circuit (the circuit of Fig. 3, wherein the circuit of Fig. 15 replaces the circuit of 60 of Fig. 3, see Col. 3 lines 55-57 and Col. 16 lines 27-34, and wherein the circuit of Fig. 18 replaces 42 of 40 of Fig. 3, see Col. 16 line 62 to Col. 17 line 2. See also combined circuit in Examiner’s Markup of Iriarte, “Markup1” hereinafter) comprising:
- a leading depletion-mode transistor (42-1 of Fig. 18, note 42-1 has a thick line and is thus anticipated as being a depletion mode transistor, see Col. 7 line 66 to Col. 8 line 2), a drain of which is connected to a voltage source (e.g., 30 see the markup),
- a trailing depletion-mode transistor (42-4 of Fig. 18, wherein Fig. 18 is used in place of 40 of Fig. 3, see the markup. Note 42-4 has a thick line and is thus anticipated as being a depletion mode transistor, see Col. 7 line 66 to Col. 8 line 2), a source of which is connected to a terminal of a first dipole (source connected to a terminal of dipole R1), and a gate of which is connected to a second terminal of the first dipole (gate of 42-4 connected to the other terminal of dipole R1),
- a connecting quadrupole (42-2 with 42-3 of Fig. 18), consists of n elementary quadrupoles, with n = 1, each elementary quadrupole comprising two depletion-mode transistors: a top transistor (42-2) and a bottom transistor (42-3), the source of the top transistor being connected to the drain of the bottom transistor (source and drain connected as claimed) and to a first terminal of the elementary quadrupole (Q1 of Markup1), the drain of the top transistor being connected to a second terminal of the elementary quadrupole (Q2 of Markup1), the gate of the bottom transistor being connected to a third terminal of the elementary quadrupole (Q3 of Markup1), and the gate of the top transistor and the source of the bottom transistor being connected to a fourth terminal of the elementary quadrupole (Q4 of Markup1);
a first terminal of the connecting quadrupole being connected to the gate of the leading transistor (Q1 connected to the gate of the leading transistor 42-1 of Markup1), a second terminal of the connecting quadrupole being connected to the source of the leading transistor (source of the leading transistor connected to Q2 of Markup1), a third terminal of the connecting quadrupole being connected to the source of the trailing transistor (source of the trailing transistor connected to Q3 of Markup 1) and a fourth terminal of the connecting quadrupole being connected to the drain of the trailing transistor (drain of the trailing transistor connected to Q4 of Markup 1), the reference voltage being supplied to the source of the leading transistor (the reference is supplied from the source of the leading transistor)
- a base enhancement-mode transistor (one of 62-1 to 62-4 of Fig. 15 when used as 60 of Fig. 3, e.g., 62-4, see the markup), the source of which is connected to a ground (sources connected to 0V either directly or via at least one other 62-2 to 6-4, see the markup), and the gate of which is connected to its drain (gate and drains of each of 62-1 to 62-4 are connected), said drain being connected to a second terminal of a second dipole (either directly or via at least one of 62-3 to 62-1, the “second dipole” being a short circuit between the resistor and 62-1. Applicant suggests the dipole being a short, see Fig. 3 of Applicant’s instant drawings. Furthermore, the second dipole may be at least another one of 62-1 to 62-4 that is not the “base enhancement-mode” transistor), the first terminal of which is connected to the second terminal of the first dipole (the first terminal of the above dipoles are connected to the second terminal of R1),
wherein the first dipole is a resistor (R1 is a resistor).
Iriarte et al. explicitly shows in the combination of the circuitry of Figs. 15 and 18 that includes more than 1 (i.e., n>1) elementary quadrupoles. Furthermore, it is noted that Iriarte et al. discloses the second dipole comprising “n” enhancement mode transistors, since “n” is equal to one and Iriarte et al. comprises more than one enhancement mode transistors in the second dipole.
Thus, Iriarte et al. fails to explicitly show, in the combined circuitry of Figs. 15 and 18, wherein the connected quadrupole “consists of n elementary quadrupoles, with n > 1” “the elementary quadrupoles being connected in series, with two consecutive elementary quadrupoles connected such that the first terminal of one elementary quadrupole is connected to the third terminal of the preceding elementary quadrupole and the second terminal of said one elementary quadrupole is connected to the fourth terminal of the preceding elementary quadrupole; and the first and the second terminals of the first elementary quadrupole forming the first and the second terminals of the connecting quadrupole, and the third and the fourth terminals of the last elementary quadrupole forming the third and the fourth terminals of the connecting quadrupole” and “wherein the second dipole comprises n enhancement-mode transistors, each of said transistors having its gate connected to its drain, said transistors being connected in series, two consecutive transistors being connected by the source of one and the drain of the other, the drain of the first transistor forming the first terminal of the second dipole and the source of the last transistor forming the second terminal of the second dipole”.
Nevertheless, Iriarte et al. suggests that there may be an arbitrary amount (i.e., “N”) transistors of 62-1 to 62-4 of Fig. 15 for the purpose of providing a desired voltage drop level and thus a desired output voltage value (see Col. 16 lines 30-32: “N transistor connected in series would give a voltage drop of NVgs2(I), in which N is a positive integer”) and/or temperature characteristics of the output voltage (see Fig. 2 and Col. 6 line 58 to Col. 7 line 12). It is further noted that the amount of transistors within the circuit of Fig. 18 is suggested by Iriarte et al. to be selected to any given amount to provide a desired output voltage level (see Col. 16 line 62 to Col. 17 line 2). Additionally, Irate et al. provides the technique for replacing the single transistor 42 of Fig. 3 with multiple transistors “split into a plurality of devices” by connecting multiple transistors “so than any given transistor has an effective sourced resistance formed by the next series connected transistor or by the resistor R1”. Thus, providing the interleaved connections source and drain terminals of each 42-1 to 42-4 with R1 and the gate of each upper transistor to the source of the next lower transistor (e.g., gate of 42-1 to source of 42-2, gate 42-2 to source of 42-3, gate of 42-3 to source of 42-4 and gate of the last transistor, i.e., 42-4 to the other terminal of resistor R1). Therefore, it can be seen that the method of splitting the first transistor into multiple transistors is clearly evidenced by Iriarte et al. and may be used to set the value to any desired amount of transistors.
It would have been obvious to select the amount of transistors within Fig. 18 of Iriarte et al. Using the technique of connecting multiple transistors “so that any given transistor has an effective sourced resistance formed by the next series connected transistor or by the resistor R1” as evidenced by Iriarte et al. Such that the circuit comprises at least n elementary quadrupoles, with n>1. For instance, in an example case, splitting the first transistor 41 into six transistors (which will cause two elementary quadrupoles as can be seen above in the Examiner’s Markup of the modified combination of Figs. 15 and 18, “Markup2” hereinafter), since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to set the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
It is further noted removal/omission of elements is known in the art since it has been held that omission of an element and its function in a combination where the remaining elements perform the same functions as before involves only routine skill in the art. In re Karlson, 136 USPQ 184. Moreover, the duplication of elements is also known, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore it would have been obvious to add and/or remove any desired number of the transistors of Figs. 15 and Fig. 18 within the circuit of Fig. 3 for the purpose of setting the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
As modified above the connecting quadrupole (see Markup2), consists of n elementary quadrupoles, with n > 1 (n equals two see first quadrupole and second quadrupole of Markup2), each elementary quadrupole comprising two depletion-mode transistors (6-2 with 6-3; 6-4 with 6-5 note thick lines for depletion): a top transistor (6-2; 6-4) and a bottom transistor (6-3; 6-5), the source of the top transistor being connected to the drain of the bottom transistor and to a first terminal of the elementary quadrupole (at Q1 and Q1-2, respectively), the drain of the top transistor being connected to a second terminal of the elementary quadrupole (at Q2 and Q2-2, respectively), the gate of the bottom transistor being connected to a third terminal of the elementary quadrupole (at Q3 and Q3-2, respectively), and the gate of the top transistor and the source of the bottom transistor being connected to a fourth terminal of the elementary quadrupole (at Q4 and Q4-2, respectively);
the elementary quadrupoles being connected in series (the first and second quadrupoles are serially connected), with two consecutive elementary quadrupoles connected such that the first terminal of one elementary quadrupole is connected to the third terminal of the preceding elementary quadrupole (Q1-2 is connected to Q3) and the second terminal of said one elementary quadrupole is connected to the fourth terminal of the preceding elementary quadrupole (Q2-2 connected to Q4); and
the first and the second terminals of the first elementary quadrupole forming the first and the second terminals of the connecting quadrupole (Q1 and Q2 are the first and second terminals of the connecting quadrupole, i.e., the combination of the first and second), and the third and the fourth terminals of the last elementary quadrupole forming the third and the fourth terminals of the connecting quadrupole (Q3-2 and Q4-2 are the third and fourth terminals of the connecting quadrupole, i.e., the combination of the first and second),
a first terminal of the connecting quadrupole being connected to the gate of the leading transistor (Q1 to the gate of 6-1), a second terminal of the connecting quadrupole being connected to the source of the leading transistor (Q2 to the source of 6-1), a third terminal of the connecting quadrupole being connected to the source of the trailing transistor (Q3-2 connected to the source of 6-6) and a fourth terminal of the connecting quadrupole being connected to the drain of the trailing transistor (Q4-2 connected to the drain of 6-6), the reference voltage being supplied to the source of the leading transistor (the reference voltage is output from the source of 6-1),
- a base enhancement-mode transistor (e.g., 62-4 of Fig. 15/Markup2), the source of which is connected to a ground (source is grounded), and the gate of which is connected to its drain (gate and drains are shorted), said drain being connected to a second terminal (source terminal of 62-3 of Fig. 15/Markup2) of a second dipole (at least two of 62-3 to 62-1 of Fig. 15/Markup2), the first terminal of which is connected to the second terminal of the first dipole (other terminal of R1, note 62-1 is directly connected to R1 and 62-2 is connected to the other terminal of R1 via 62-1), wherein the second dipole comprises n enhancement-mode transistors (the second dipole comprises at least two transistor), each of said transistors having its gate connected to its drain (each of 62-3 to 62-1 have a gate and drain shorted), said transistors being connected in series (the transistors are serially connected), two consecutive transistors being connected by the source of one and the drain of the other (source and drains are connected), the drain of the first transistor forming the first terminal of the second dipole (one of 62-1 and 62-2 forms the first terminal of the second dipole) and the source of the last transistor forming the second terminal of the second dipole (source of 62-3 forms the last transistor of the second dipole). Therefore the circuit, as modified in Markup2, is connected as claimed.
With respect to claim 5, a voltage reference circuit according to claim 1,characterized in that the depletion-mode and enhancement-mode transistors are GaN transistors or MOS transistors (the transistors are NMOS transistors, see Col. 1 line 66 to Col. 2 line 2).
With respect to claim 11, Markup discloses four enhancement mode transistors 62-1 to 62-4 and six depletion mode transistors 6-1 to 6-6. Nevertheless, the above modification of claim 1 stated that any amount transistor can be selected in each of Figs. 15 and 18 to provide a desired output level. While Markup2 fails to explicitly show that “the circuit comprises exactly twice as many depletion mode transistors as enhancement-mode transistors”. It would have been obvious to remove one of 62-1 to 62-4 (i.e., have three enhancement mode devices), such that “the circuit comprises exactly twice as many depletion mode transistors as enhancement-mode transistor” since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). One would have been motivated to do so to set the desired voltage drop, temperature characteristic and/or reference voltage output value to a desired level, since the amount of transistors control the above variables according to the amount of devices selected as suggested and evidenced by Iriarte et al.
With respect to claim 12, a voltage reference circuit according to claim 1, wherein the depletion-mode and enhancement mode transistors are N-channel transistors (all of the transistors are N-channel transistors, i.e., NMOS transistors, see Col. 1 line 66 to Col. 2 line 2).
Response to Arguments
Applicant's arguments filed 4/28/2026 have been fully considered but they are not persuasive.
In summary Applicant argues that, at best, the combination of Figs. 15 and 18 of Iriarte et al. discloses a single quadrupole (i.e., as connection as shown in Fig. 18). Iriarte et al. fails to disclose multiple (e.g. two) quadrupoles serially connected and having the terminals interconnected with each other as recited in claim 1. Applicant further argues assuming, arguendo, that one may add additional (or adjust the amount of) transistors in each of Figs. 15 and 18 to set a desired reference voltage level. Iriarte et al. fails to provide any evidence for connecting at least two quadrupoles having terminals interconnected as recited in claim 1, and even when adding additional transistors one would fail to arrive at the claimed invention.
Examiner disagrees with Applicant’s arguments. This is because Iriarte et al. anticipates adjusting the reference voltage by changing the amount of transistors to any desired amount. For instance, Iriarte et al. states, in Col. 16 lines 28-29 that “[t]he voltage contribution from each stage may also be varied” (Examiner’s emphasis). The first stage is that of stage 40 (see Col. 16 lines 35-36) and the second stage is that of 60 (see Col. 16 lines 28-30). Moreover, Iriarte et al. discloses that the voltage contributions (i.e., Vgs2 and -Vgs1, see equation at line 40 of Col. 16) may be varied according to the amount of transistors within each of the second stage (see Col. 16 lines 30-34) and first stage (see Col 16 lines 62 to Col. 17 line 2). Therefore, it can be seen that the value of Vout is a result of the effective values of Vgs2 and -Vgs1, wherein Vgs2 and -Vgs1 of stages 60 and 40 may be varied according to the amount of devices in each stage to generate the desired Vout value. Thus, it would be obvious to select any amount of transistors within 60 and 40 of Figs. 15 and 18 to generate a desired value of Vout.
Examiner agrees, that Fig. 18 of Iriarte et al. explicitly discloses the use of four transistors and will thus fail to disclose that n>1 (or that n=2). However, Fig. 18 merely provides for the example of splitting the first transistor into four devices (i.e., transistors). Furthermore, Fig. 18 provides for the understanding of how to spilt the single transistor into four transistors in the interleaved fashion as shown in Fig. 4. Furthermore, Iriarte et al. provides the technique for replacing the single transistor 42 of Fig. 3 with multiple transistors “split into a plurality of devices” by connecting multiple transistors “so that any given transistor has an effective sourced resistance formed by the next series connected transistor or by the resistor R1”. Thus, providing the interleaved connections source and drain terminals of each 42-1 to 42-4 with R1 and the gate of each upper transistor to the source of the next lower transistor (e.g., gate of 42-1 to source of 42-2, gate 42-2 to source of 42-3, gate of 42-3 to source of 42-4 and gate of the last transistor, i.e., 42-4 to the other terminal of resistor R1). Therefore, it can be seen that the method of splitting the first transistor into multiple transistors is clearly evidenced by Iriarte et al. and may be used to set the value to any desired amount of transistors. When selecting the first transistor to be split into six devices the circuit of Iriarte et al. will be connected as recited in claim 1. The six devices will have the connections as shown in Markup2 above such that two quadrupoles are serially connected and have first through fourth terminals connected as claimed. Thus, Iriarte et al. will be connected as claimed when the first transistor is split into six devices using the method of splitting as shown and described in Fig. 18. Additionally, Iriarte et al. anticipates constructing the device such that any amount of diode connected transistors of Fig. 15 may be used. Thus, by selecting a desired ratio between the transistors of Fig. 18 and the transistors of Fig. 15 to provide a desired reference voltage level one will arrive at the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F.
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2836
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