DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/30/2025 has been entered.
Response to Amendment
This office action is in response to the amendment filed on 12/01/2025. Claims 1, 3-4, 6-10, 14-16, and 32-33 are pending. Claims 1, 3, 6-9, 14, 16, and 32 are amended. Claims 2, 5, 11-13, and 17-31 are canceled. Examiner notes that claim 10 is marked as “Currently Amended” but does not appear to have been amended and claim 14 is marked as “Previously Presented” but has been amended.
Response to Arguments
Applicant’s argument on page 10 of the Remarks filed 12/01/2025, with respect to the rejection(s) of claim(s) 1 under 35 USC 102 that the translation fault of Abhishek is different from the detected interrupt event recited in the claims have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Mahurin US 2018/0081687.
Claim Objections
Claims 1, 16, and 32 are objected to because of the following informalities:
Claim 1 line 6- delete the comma before “and”
the same corrections should be made in claims 16 and 32
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4, 6-10, 14-16, and 32-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a detected interrupt event” in lines 5-6 and “an interrupt event” in line 6. It is unclear whether these refer to the same interrupt event or if they are different. For purposes of examination, they will be interpreted as the same.
Claims 16 and 32 recite the same limitations and are unclear for the same reasons.
Claim 1 recites “a detected barrier instruction” in line 6 and “a barrier instruction” in lines 7-8. It is unclear whether these refer to the same barrier instruction or if they are different. For purposes of examination, they will be interpreted as the same.
Claims 16 and 32 recite the same limitations and are unclear for the same reasons.
Claim 1 recites “detecting an event during processing of the N load/store operations that renders the vector load/store instruction non-atomic” in lines 4-5 and “having none of the N load/store operations produce any processing effect, or having the N load/store operations all produce processing effects” in lines 9-10. By having none of the N load/store operations produce any processing effect or having the N load/store operations all produce processing effects, the vector load/store instruction is understood to be atomic. It is thus unclear how the vector load/store instruction may be rendered non-atomic while also being atomic. For purposes of examination, this limitation will be interpreted as “detecting an event during processing of the N load/store operations”.
Claims 16 and 32 recite the same limitations and are unclear for the same reasons.
Claim 3 recites “the interrupt event” in line 5 and line 6. It is unclear which interrupt event in claim 1 this refers to. For purposes of examination, this interrupt event and the interrupt events in claim 1 are interrupt as the same interrupt event.
Claim 6 recites “the interrupt event” in the last line. It is unclear which interrupt event in claim 1 this refers to. For purposes of examination, this interrupt event and the interrupt events in claim 1 are interrupt as the same interrupt event.
Claim 7 recites “the interrupt event” in the last line. It is unclear which interrupt event in claim 1 this refers to. For purposes of examination, this interrupt event and the interrupt events in claim 1 are interrupt as the same interrupt event.
Claim 8 recites “the interrupt event” in the last line. It is unclear which interrupt event in claim 1 this refers to. For purposes of examination, this interrupt event and the interrupt events in claim 1 are interrupt as the same interrupt event.
Claim 9 recites “the interrupt event” in the last line. It is unclear which interrupt event in claim 1 this refers to. For purposes of examination, this interrupt event and the interrupt events in claim 1 are interrupt as the same interrupt event.
Claim 14 recites “the barrier instruction” in lines 4, 8, 11, and 13. It is unclear which barrier instruction in claim 1 this refers to. For purposes of examination, this barrier instruction and the barrier instruction in claim 1 are interrupt as the same barrier instruction
Claims dependents on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-10, 14-15, and 32-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mahurin US 2018/0081687.
Regarding claim 1, Mahurin teaches:
1. An atomicity retaining method, comprising:
generating N load/store operations from a vector load/store instruction, wherein N is a positive integer greater than or equal to 1 ([0018]: the SIMD scatter instruction 114 is executed to store each component of a vector to a different address in memory, which generates a store operation for storing each of the components (i.e., N store operations));
detecting an event during processing of the N load/store operations that renders the vector load/store instruction non-atomic, wherein the event comprises at least one of a detected interrupt event, and a detected barrier instruction, wherein an interrupt event is an event from outside a central processing unit (CPU) executing instruction, and a barrier instruction is an instruction used to ensure synchronization between different operations ([0027]: the processor may wait to perform the scatter store-release operation until completion of the SIMD scatter instruction 114, which involves detecting the scatter store-release before completion/during processing the SIMD scatter instruction 114 (to know that it has to wait), and the scatter store-release operation is a barrier instruction since it ensures synchronization between different memory operations by enabling a particular memory operation to complete before initiating another memory operation, see [0028]); and
having none of the N load/store operations produce any processing effect, or having the N load/store operations all produce processing effects; wherein the having none of the N load/store operations produce any processing effect comprises: a load/store operation of the N load/store operations being executed but not committed or none of the N load/store operations being executed or none of the N load/store operations being issued and the having the N load/store operations all produce processing effects comprises: all the N load/store operations being executed and all execution results of the N load/store operations are committed ([0027]: execution of the release instruction waits until completion of the SIMD scatter operation 114, which defers updating the architectural state of the memory 160 until completion of the SIMD scatter operation, see also [0024] disclosing that the SIMD scatter instruction 114 stores data to memory 160; that is, completion of the SIMD scatter instruction includes having all the store operations of the SIMD scatter instruction executed and storing/committing all the results to the memory).
Regarding claim 3, Mahurin teaches:
3. The method according to claim 1, wherein before detecting the event during the processing of the N load/store operations that renders the vector load/store instruction non-atomic, the method further comprises:
adding an interrupt identifier to one or more of the N load/store operations, in response to an occurrence of the interrupt event, during processing of the vector load/store instruction(since the claim does not require the interrupt event and this limitation is contingent on an occurrence of the interrupt event, this limitation is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04(II));
wherein the interrupt identifier is used to indicate the occurrence of the interrupt event during the processing of the vector load/store instruction (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 4, Mahurin teaches:
4. The method according to claim 3, wherein adding the interrupt identifier to one or more of the N load/store operations comprises:
adding the interrupt identifier to any one of the N load/store operations; or adding the interrupt identifier to all the N load/store operations (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 6, Mahurin teaches:
6. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations that renders the vector load/store instruction non-atomic comprises:
examining the N load/store operations in turn to detect a load/store operation of the N load/store operations marked with the interrupt identifier (this limitation is not required since it follows from the contingent limitation in claim 3 which marks the N load/store operations with the interrupt identifier, which is not required under BRI);
wherein in the case that there is the event that renders the vector load/store instruction non-atomic, having none of the N load/store operations produce any processing effect comprises:
if any one of the N load/store operations is marked with the interrupt identifier, caching the N load/store operations generated from the vector load/store instruction without executing any thereof, until the interrupt event is handled (this limitation is not required since it follows from a limitation that is not required under BRI).
Regarding claim 7, Mahurin teaches:
7. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations that renders the vector load/store instruction non-atomic comprises:
examining the N load/store operations in turn to detect a load/store operation of the N load/store operations marked with the interrupt identifier (this limitation is not required since it follows from the contingent limitation in claim 3 which marks the N load/store operations with the interrupt identifier, which is not required under BRI);
wherein in the case that there is the event that renders the vector load/store instruction non-atomic, having the N load/store operations all produce processing effects comprises:
if any one of the N load/store operations is marked with the interrupt identifier, executing all the N load/store operations (this limitation is not required since it follows from a limitation that is not required under BRI);
committing the execution results of the N load/store operations (the SIMD scatter instruction stores its data to memory, which commits execution results of the store operations, see [0024] and [0027]); and
when it is determined that all the execution results of the N load/store operations have been
committed, handling the interrupt event (this limitation is not required since it follows from a limitation that is not required under BRI).
Regarding claim 8, Mahurin teaches:
8. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations that renders the vector load/store instruction non-atomic comprises:
detecting whether a foremost load/store operation of the N load/store operations is marked with the interrupt identifier (this limitation is not required since it follows from a limitation that is not required under BRI);
wherein in the case that there is the event that renders the vector load/store instruction non-atomic, having none of the N load/store operations produce any processing effect comprises:
if the foremost load/store operation is marked with the interrupt identifier, caching the N load/store operations generated from the vector load/store instruction without executing any thereof, until the interrupt event is handled (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI).
Regarding claim 9, Mahurin teaches:
9. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations that renders the vector load/store instruction non-atomic comprises:
detecting whether a foremost load/store operation of the N load/store operations is marked with the interrupt identifier (this limitation is not required since it follows from a limitation that is not required under BRI);
wherein in the case that there is the event that renders the vector load/store instruction non-atomic, having the N load/store operations all produce processing effects comprises:
if the foremost load/store operation is marked with the interrupt identifier, executing all the N load/store operations (this limitation is not required since it follows from a limitation that is not required under BRI);
committing the execution results of the N load/store operations (the SIMD scatter instruction stores its data to memory, which commits execution results of the store operations, see [0024] and [0027]); and
when it is determined that all the execution results of the N load/store operations have been committed, handling the interrupt event (this limitation is not required since it follows from a limitation that is not required under BRI).
Regarding claim 10, Mahurin teaches:
10. The method according to claim 3, further comprising:
if none of the N load/store operations is marked with an interrupt identifier, executing the N load/store operations (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI); and
committing execution results of the N load/store operations (the SIMD scatter instruction stores its data to memory, which commits execution results of the store operations, see [0024] and [0027]).
Regarding claim 14, Mahurin teaches:
14. The method according to claim 1, wherein detecting the event during the processing of the N load/store operations that renders the vector load/store instruction non-atomic comprises:
detecting whether the barrier instruction is received ([0026]: the processor may execute the scatter store-release instruction (i.e., the barrier instruction), which involves detecting whether it was received);
wherein in the case that there is the event that renders the vector load/store instruction non- atomic, having none of the N load/store operations produce any processing effect, or having the N load/store operations all produce processing effects comprises:
in response to receiving the barrier instruction (this limitation is not required since it is contingent on receiving the barrier instruction, which is not required under BRI of the claims (the claims only require detecting whether the barrier is received)), processing the barrier instruction when it is determined that all the N load/store operations being processed have been executed and the execution results of the N load/store operations have been committed; or
in response to obtaining the vector load/store instruction, caching, if the barrier instruction is in process, the N load/store operations generated from the vector load/store instruction without executing any thereof, until processing of the barrier instruction is over (this limitation is not required since it is contingent on obtaining the vector load/store instruction and the barrier instruction being in process, which is not required under BRI of the claims).
Regarding claim 15, Mahurin teaches:
15. The method according to claim 1, wherein the vector load/store instruction is a Load instruction or a Store instruction ([0018]: the SIMD scatter instruction is a store instruction since it stores data to memory);
when the vector load/store instruction is the Load instruction, executing the N load/store operations (this limitation is contingent on the vector load/store instruction being a load instruction, which is not required under BRI) comprises:
executing an operation of reading operand at an address indicated by the vector load/store instruction from a memory to a designated general-purpose register;
when the vector load/store instruction is the Store instruction, executing the N load/store operations comprises:
executing an operation of writing the operand at the address indicated by the vector load/store instruction from the designated general-purpose register to the memory (this limitation is not required since follows for there being a designated general-purpose register which is not required by the claim).
Regarding claim 32, Mahurin teaches:
32. An electronic device, comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and cause one or more processors to:
obtain a vector load/store instruction, and generate N load/store operations from the vector load/store instruction, wherein N is a positive integer greater than or equal to 11 ([0018]: the SIMD scatter instruction 114 is executed to store each component of a vector to a different address in memory, which involves obtaining the SIMD scatter instruction and generating a store operation for storing each of component (i.e., N store operations)); and
detect an event during processing of the N load/store operations that renders the vector load/store instruction non-atomic, wherein the event comprises at least one of a detected interrupt event, and a detected barrier instruction, wherein an interrupt event is an event from outside a central processing unit (CPU) executing instruction, and a barrier instruction is an instruction used to ensure synchronization between different operations ([0027]: the processor may wait to perform the scatter store-release operation until completion of the SIMD scatter instruction 114, which involves detecting the scatter store-release before completion/during processing the SIMD scatter instruction 114 (to know that it has to wait), and the scatter store-release operation is a barrier instruction since it ensures synchronization between different memory operations by enabling a particular memory operation to complete before initiating another memory operation, see [0028]); and have none of the N load/store operations produce any processing effect, or have the N load/store operations all produce processing effects; wherein the having none of the N load/store operations produce any processing effect comprises: a load/store operation of the N load/store operations being executed but not committed, or none of the N load/store operations being executed, or none of the N load/store operations being issued, and the having the N load/store operations all produce processing effects comprises: all the N load/store operations being executed and all execution results of the N load/store operations are committed ([0027]: execution of the release instruction waits until completion of the SIMD scatter operation 114, which defers updating the architectural state of the memory 160 until completion of the SIMD scatter operation, see also [0024] disclosing that the SIMD scatter instruction 114 stores data to memory 160; that is, completion of the SIMD scatter instruction includes having all the store operations of the SIMD scatter instruction executed and storing/committing all the results to the memory).
Regarding claim 33, Mahurin teaches:
33. A non-transitory processor-readable storage medium storing a computer program, wherein the computer program is configured to enable a processor to execute the atomicity retaining method according to claim 1 ([0010] discloses a non-transitory computer readable medium storing instructions executable to perform operations by a processor including performing the SIMD scatter operation (i.e., a program configured to enable a processor to execute the method of claim 1)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Mahurin US 2018/0081687 in view of Fleischer US 2014/0040596.
Regarding claim 15, Mahurin teaches:
15. The method according to claim 1, wherein the vector load/store instruction is a Load instruction or a Store instruction ([0018]: the SIMD scatter instruction is a store instruction since it stores data to memory);
when the vector load/store instruction is the Load instruction, executing the N load/store operations (this limitation is contingent on the vector load/store instruction being a load instruction, which is not required under BRI) comprises:
executing an operation of reading operand at an address indicated by the vector load/store instruction from a memory to a designated general-purpose register;
when the vector load/store instruction is the Store instruction, executing the N load/store operations comprises:
executing an operation of writing the operand at the address indicated by the vector load/store instruction to the memory ([0018]: the SIMD scatter instruction writes components of a vector/operand at an address indicated by the instruction to memory).
Mahurin does not teach executing the SIMD scatter instruction to store from the designated general-purpose register to the memory.
However, Fleischer teaches a scatter instruction that stores data from a register file entry (i.e., a designated register) to memory, see [0062]-[0064], see also [0050] disclosing that the register files supports different size data types which indicates that the registers are general-purpose registers.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the scatter instruction of Mahurin to support writing data from a designated general-purpose register to memory as taught by Fleischer. One of ordinary skill in the art would have been motivated to make this modification to improve flexibility by enabling writing data from a register to memory.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Mahurin US 2018/0081687 in view of Abhishek US 2023/0017802.
Regarding claim 16, Mahurin teaches:
16. A processor, comprising:
a vector load/store instruction, and generate N load/store operations from the vector load/store instruction, wherein N is a positive integer greater than or equal to 1 ([0018]: the SIMD scatter instruction 114 is executed to store each component of a vector to a different address in memory, which generates a store operation for storing each of component (i.e., N store operations)); and
a processing circuitry, configured to detect an event during processing of the N load/store operations that renders the vector load/store instruction non-atomic, wherein the event comprises at least one of a detected interrupt event, and a detected barrier instruction, wherein an interrupt event is an event from outside a central processing unit (CPU) executing instruction, and a barrier instruction is an instruction used to ensure synchronization between different operations ([0027]: the processor may wait to perform the scatter store-release operation until completion of the SIMD scatter instruction 114, which involves detecting the scatter store-release before completion/during processing the SIMD scatter instruction 114 (to know that it has to wait), and the scatter store-release operation is a barrier instruction since it ensures synchronization between different memory operations by enabling a particular memory operation to complete before initiating another memory operation, see [0028]); and have none of the N load/store operations produce any processing effect, or have the N load/store operations all produce processing effects; wherein the having none of the N load/store operations produce any processing effect comprises: a load/store operation of the N load/store operations being executed but not committed, or none of the N load/store operations being executed, or none of the N load/store operations being issued, and the having the N load/store operations all produce processing effects comprises: all the N load/store operations being executed and all execution results of the N load/store operations are committed ([0027]: execution of the release instruction waits until completion of the SIMD scatter operation 114, which defers updating the architectural state of the memory 160 until completion of the SIMD scatter operation, see also [0024] disclosing that the SIMD scatter instruction 114 stores data to memory 160; that is, completion of the SIMD scatter instruction includes having all the store operations of the SIMD scatter instruction executed and storing/committing all the results to the memory).
Mahurin does not explicitly teach a decoder configured to obtain the vector load/store instruction and generate N load/store operations.
However, Abhishek teaches a decoder that decodes a load/store instruction to generate load/store uops, see [0077].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Mahurin to include a decoder for decoding the vector load/store instruction to generate load/store operations as taught by Abhishek. One of ordinary skill in the art would have been motivated to make this modification because decoding instructions is a known technique on the known device of a processor for generating operations for performing the instruction and would yield the predictable result of enabling instructions to be executed by the processor.
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183