DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 04/28/2026. Claims 1, 3-4, 6-10, 15-16, and 32-33 are pending. Claims 1, 3, 6-9, 16, and 32 are amended. Claims 2, 5, 11-14, and 17-31 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks page 10-11, filed 04/28/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Specifically, the argument that “Mahurin is silent about the detected interrupt event, which is an event from outside a central processing unit (CPU)” was found to be persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made over Abhishek US 2023/0017802 in view of McKenney US 2015/0074311.
Claim Objections
Claims, 1, 16, and 32 are objected to because of the following informalities:
Claim 1 line 7- “instruction” should be “instructions” (plural). Alternatively, the phrase “executing instruction” may be deleted to clarify that the detected interrupt event is an event from outside a CPU.
similar corrections should be made for claims 16 and 32.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6-10, 15-16, and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Abhishek US 2023/0017802 in view of McKenney US 2015/0074311.
Regarding claim 1, Abhishek teaches:
1. An atomicity retaining method, comprising:
generating N load/store operations from a vector load/store instruction, wherein N is a positive integer greater than or equal to 1 ([0077]: the decoder generates load/store uops from a single-copy-atomic load/store instruction, which is a vector load/store instruction since it loads or stores a block/vector of data, see [0015]);
detecting an event during processing of the N load/store operations ([0083]: step 156 detects whether there is a translation fault/exception event during the processing of a first one of the load micro-operations (see also Fig. 9)); and
having none of the N load/store operations produce any processing effect (Fig. 9: S158 aborts the access, which causes none of the uops to produce any processing effect), or having the N load/store operations all produce processing effects; wherein the having none of the N load/store operations produce any processing effect comprises: a load/store operation of the N load/store operation being executed but not committed or none of the N load/store operations being executed (Fig. 9: S158 aborts the access, which causes none of the uops to be executed) or none of the N load/store operations being issued and the having the N load/store operations all produce processing effects comprises: having all the N load/store operations being executed and all execution results of the N load/store operations are committed.
Abhishek does not teach:
wherein the event comprises a detected interrupt event, wherein the detected interrupt event is an event from outside a central processing unit (CPU) executing instruction
However, McKenney teaches aborting a transaction in response to detecting a fatal signal interrupt that is generated from a user input (i.e., an event from outside the CPU), see [0020]-[0022].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abhishek’s exception detection/handling to include detecting/handling fatal signal interrupts from outside the CPU as taught by McKenney. One of ordinary skill in the art would have been motivated to make this modification to improve user control by allowing users to abort execution of a process (McKenney [0020]).
Regarding claim 3, Abhishek in view of McKenney teaches:
3. The method according to claim 1, wherein before detecting the event during the processing of the N load/store operations, the method further comprises:
adding an interrupt identifier to one or more of the N load/store operations, in response to an occurrence of the detected interrupt event, during processing of the vector load/store instruction (since this limitation is contingent on an occurrence of the interrupt event (before detecting the event), this limitation is a contingent limitation that is not required under BRI of a method claim, see MPEP 2111.04(II));
wherein the interrupt identifier is used to indicate the occurrence of the detected interrupt event during the processing of the vector load/store instruction (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 4, Abhishek in view of McKenney teaches:
4. The method according to claim 3, wherein adding the interrupt identifier to one or more of the N load/store operations comprises:
adding the interrupt identifier to any one of the N load/store operations (this limitation is not required since it follows from a contingent limitation that is not required under BRI); or
adding the interrupt identifier to all the N load/store operations (this limitation is not required since it follows from a contingent limitation that is not required under BRI).
Regarding claim 6, Abhishek in view of McKenney teaches:
6. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations comprises:
examining the N load/store operations in turn to detect a load/store operation of the N load/store operations marked with the interrupt identifier (this limitation is not required since it follows from the contingent limitation in claim 3 which marks the N load/store operations with the interrupt identifier, which is not required under BRI);
wherein in the case that there is the detected interrupt event, having none of the N load/store operations produce any processing effect comprises:
if any one of the N load/store operations is marked with the interrupt identifier, caching the N load/store operations generated from the vector load/store instruction without executing any thereof, until the detected interrupt event is handled (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI).
Regarding claim 7, Abhishek in view of McKenney teaches:
7. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations comprises:
examining the N load/store operations in turn to detect a load/store operation of the N load/store operations marked with the interrupt identifier (this limitation is not required since it follows from the contingent limitation in claim 3 which marks the N load/store operations with the interrupt identifier, which is not required under BRI);
wherein in the case that there is the detected interrupt event, having the N load/store operations all produce processing effects comprises:
if any one of the N load/store operations is marked with the interrupt identifier, executing all the N load/store operations (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI);
committing the execution results of the N load/store operations (since this limitation follows from a limitation that is not required by the claims, this limitation is also not required); and
when it is determined that all the execution results of the N load/store operations have been
committed, handling the detected interrupt event (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI).
Regarding claim 8, Abhishek in view of McKenney teaches:
8. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations comprises:
detecting whether a foremost load/store operation of the N load/store operations is marked with the interrupt identifier (this limitation is not required since it follows from the contingent limitation in claim 3 which marks the N load/store operations with the interrupt identifier, which is not required under BRI);
wherein in the case that there is the detected interrupt event, having none of the N load/store operations produce any processing effect comprises:
if the foremost load/store operation is marked with the interrupt identifier, caching the N load/store operations generated from the vector load/store instruction without executing any thereof, until the detected interrupt event is handled (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI).
Regarding claim 9, Abhishek in view of McKenney teaches:
9. The method according to claim 3, wherein detecting the event during the processing of the N load/store operations comprises:
detecting whether a foremost load/store operation of the N load/store operations is marked with the interrupt identifier (this limitation is not required since it follows from the contingent limitation in claim 3 which marks the N load/store operations with the interrupt identifier, which is not required under BRI);
wherein in the case that there is the detected interrupt event, having the N load/store operations all produce processing effects comprises:
if the foremost load/store operation is marked with the interrupt identifier, executing all the N load/store operations (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI);
committing the execution results of the N load/store operations (since this limitation follows from a limitation that is not required by the claims, this limitation is also not required); and
when it is determined that all the execution results of the N load/store operations have been committed, handling the detected interrupt event (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI).
Regarding claim 10, Abhishek in view of McKenney teaches:
10. The method according to claim 3, further comprising:
if none of the N load/store operations is marked with an interrupt identifier, executing the N load/store operations (since this limitation is contingent upon a condition that is not required by the claim, this limitation is not required under BRI); and
committing the execution results of the N load/store operations (since this limitation follows from a limitation that is not required by the claims, this limitation is also not required).
Regarding claim 15, Abhishek in view of McKenney teaches:
15. The method according to claim 1, wherein the vector load/store instruction is a Load instruction or a Store instruction ([0015] the single-copy-atomic load/store instruction is a load instruction or a store instruction);
when the vector load/store instruction is the Load instruction, executing the N load/store operations (since this limitation follows from a limitation that is not required by the claims (as claim 1 allows for none of the N load/store operations to be executed), this limitation is also not required) comprises:
executing an operation of reading operand at an address indicated by the vector load/store instruction from a memory to a designated general-purpose register;
when the vector load/store instruction is the Store instruction, executing the N load/store operations (since this limitation follows from a limitation that is not required by the claims (as claim 1 allows for none of the N load/store operations to be executed), this limitation is also not required) comprises:
executing an operation of writing the operand at the address indicated by the vector load/store instruction from the designated general-purpose register to the memory.
Regarding claim 16, Abhishek teaches:
16. A processor, comprising:
a decoder, configured to obtain a vector load/store instruction, and generate N load/store operations from the vector load/store instruction, wherein N is a positive integer greater than or equal to 1 ([0077]: the decoder generates load/store uops from obtaining a single-copy-atomic load/store instruction, which is a vector load/store instruction since it loads or stores a block/vector of data, see [0015]); and
a processing circuitry, configured to detect an event during processing of the N load/store operations ([0083]: the MMU (i.e., processing circuitry) at step 156 detects whether there is a translation fault/exception event during the processing of a first one of the load micro-operations (see also Fig. 9)); and have none of the N load/store operations produce any processing effect ([0083]: if there is a translation fault/exception event, the access is aborted at step 158 and the remaining load uops are prevented from being processed), or have the N load/store operations all produce processing effects; wherein the having none of the N load/store operations produce any processing effect comprises: a load/store operation of the N load/store operations being executed but not committed, or none of the N load/store operations being executed ([0083]: preventing the remaining load uops from being processed, the load uops are being not executed), or none of the N load/store operations being issued, and the having the N load/store operations all produce processing effects comprises: all the N load/store operations being executed and all execution results of the N load/store operations are committed (this “or” limitation is not required under BRI).
Abhishek does not teach:
wherein the event comprises a detected interrupt event, wherein the detected interrupt event is an event from outside a central processing unit (CPU) executing instruction
However, McKenney teaches aborting a transaction in response to detecting a fatal signal interrupt that is generated from a user input (i.e., an event from outside the CPU), see [0020]-[0022].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abhishek’s exception detection/handling to include detecting/handling fatal signal interrupts from outside the CPU as taught by McKenney. One of ordinary skill in the art would have been motivated to make this modification to improve user control by allowing users to abort execution of a process (McKenney [0020]).
Regarding claim 32, Abhishek teaches:
32. An electronic device, comprising a memory and one or more programs (Fig. 1 memory 18 stores program instructions, see [0053]), wherein the one or more programs are stored in the memory and cause one or more processors (Fig. 1 PE 4 is a processor that executes the program instructions, see [0048]) to:
obtain a vector load/store instruction, and generate N load/store operations from the vector load/store instruction, wherein N is a positive integer greater than or equal to 1 ([0077]: the decoder generates load/store uops from obtaining a single-copy-atomic load/store instruction, which is a vector load/store instruction since it loads or stores a block/vector of data, see [0015]); and
detect an event during processing of the N load/store operations ([0083]: the MMU (i.e., processing circuitry) at step 156 detects whether there is a translation fault/exception event during the processing of a first one of the load micro-operations (see also Fig. 9)); and have none of the N load/store operations produce any processing effect ([0083]: if there is a translation fault/exception event, the access is aborted at step 158 and the remaining load uops are prevented from being processed), or have the N load/store operations all produce processing effects; wherein the having none of the N load/store operations produce any processing effect comprises: a load/store operation of the N load/store operations being executed but not committed, or none of the N load/store operations being executed ([0083]: preventing the remaining load uops from being processed, the load uops are being not executed), or none of the N load/store operations being issued, and the having the N load/store operations all produce processing effects comprises: all the N load/store operations being executed and all execution results of the N load/store operations are committed (this “or” limitation is not required under BRI).
Abhishek does not teach:
wherein the event comprises a detected interrupt event, wherein the detected interrupt event is an event from outside a central processing unit (CPU) executing instruction
However, McKenney teaches aborting a transaction in response to detecting a fatal signal interrupt that is generated from a user input (i.e., an event from outside the CPU), see [0020]-[0022].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Abhishek’s exception detection/handling to include detecting/handling fatal signal interrupts from outside the CPU as taught by McKenney. One of ordinary skill in the art would have been motivated to make this modification to improve user control by allowing users to abort execution of a process (McKenney [0020]).
Regarding claim 33, Abhishek in view of McKenney teaches:
33. A non-transitory processor-readable storage medium storing a computer program (Abhishek Fig. 1 memory 18 stores program instructions, see [0053]), wherein the computer program is configured to enable a processor to execute the atomicity retaining method according to claim 1 (Abhishek Fig. 1 PE 4 is a processor that executes the program instructions, see [0048]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KASIM ALLI whose telephone number is (571)270-1476. The examiner can normally be reached Monday - Friday 9am 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached on (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KASIM ALLI/Examiner, Art Unit 2182
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
Prosecution Insights