DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-3, 7, 8, 10-12 and 16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 17-20 of U.S. Patent No. 12,563,971. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-3 and 17-20 of U.S. Patent No. 12,563,971 are clearly anticipated or similar in scope to the rejected claims 1-3, 7, 8, 10-12 and 16 of the U. S. Pat. App (No. 18/718,173) with only obvious wording variations. For example below:
Instant application
Claim Number
U.S. Patent No. 12,563,971
Claim Number
1
17
2
18
3
17
7
18
8
18, 20
10
1, 2
11
1
12
2
16
2, 3
As shown in table above, the limitations in claims 1-3, 7, 8, 10-12 and 16 of pending Application can be found the limitations in claims 1-3 and 17-20 as indicated above of U.S. Patent No. 12,563,971. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would recognize that they are not patentably distinct from each other. Accordingly, claims 1-3, 7, 8, 10-12 and 16 of pending Application are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 17-20 of U.S. Patent No. 12,563,971 for the reasons as stated above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 12, 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the gate electrode" in page 11 lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the gate electrode" in page 12 line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 16 recites the limitation "the gate electrode" in page 13 line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 17 recites the limitation "the gate electrode" in page 14 line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-13, 15, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by NPL “Developing Graphene-Based Moire Heterostructures for Twistronics” (Liu et al hereinafter Liu)
Regarding claim 1, Liu discloses an assembly (abstract, section 1. Introduction) comprising: a structure comprising a layer of a first material positioned in contact with a layer of a second material to form an interface between the first material and the second material (figs. 2, 8, section 4.5), each of the first material and the second material being selected such that a time-reversal symmetry breaking field associated with the interface is stabilized (page 16, section 5.1.2); and a control apparatus associated with the structure configured to control a ferromagnetic state associated with the interface (page 20, section 5.2.2).
Regarding claim 2, Liu also teaches wherein the control apparatus comprises one of a current source configured to provide a DC current, a gate electrode connected to a gate voltage source and configured to apply field effect gating to the interface, an electric field source configured to apply an out-of-plane electric field to the interface, and a magnetic field source configured to apply an out-of-plane magnetic field to the interface (page 20, section 5.2.2).
Regarding claim 3, Liu also teaches wherein one of the first material and the second material is twisted multi-layer graphene and an other of the first material and the second material is a transition metal dichalcogenide (page 1, section 1, page 14 section 4.5).
Regarding claim 4, Liu also teaches wherein the one of the first material and the second material is twisted trilayer graphene, and the structure and the control apparatus are configured to provide a superconducting diode having a direction of current flow for which superconducting transport behavior is exhibited (fig. 11, page 20 section 5.2.2).
Regarding claim 5, as best understood 112 2nd rejection above, Liu also teaches wherein the control interface comprises the gate electrode connected to the gate voltage source and configured to apply field effect doping to the interface to select a direction of current flow for which superconducting transport behavior is exhibited for the superconducting diode (figs, 11, 12, page 20 section 5.2.2).
Regarding claim 6, Liu also teaches wherein the control interface comprises the magnetic field source configured to apply the out-of-plane magnetic field to the interface, the magnetic field source being configured to apply the out-of-plane magnetic field with a predetermined amplitude to the interface and gradually decrease the amplitude of the out-of-plane magnetic field to zero (fig. 12b, page 20, section 5.2.2).
Regarding claim 9, Liu also teaches wherein the transition metal dichalcogenide is tungsten diselenide (page 18, section5.2.1).
Regarding claim 10, Liu discloses a method for fabricating an assembly (abstract, section 1. Introduction), the method comprising: positioning a first material in contact with a second material to form a structure with an interface between the first material and the second material (page 14, section 4.5, figs. 2, 8), each of the first material and the second material being selected such that a time-reversal symmetry breaking field is stabilized at the interface (page 16, section 5.1.2, page 21, section 5.2.3); and applying one of a DC current to the interface, an out-of-plane electric field to the interface, a magnetic field to the interface, and a voltage bias to a gate electrode associated with the interface to control a valley ferromagnetic state associated with the interface (figs. 7, 8, page 20, section 5.2.2).
Regarding claim 11, Liu also teaches wherein one of the first material and the second material is twisted multi-layer graphene and an other of the first material and the second material is a transition metal dichalcogenide (page 1, section 1, page 14 section 4.5).
Regarding claim 12, as best understood 112 2nd rejection above, Liu also teaches wherein applying the one of the DC current to the interface, the out-of-plane electric field to the interface, the magnetic field to the interface, and the voltage bias to the gate electrode associated with the interface comprises applying the magnetic field to the interface, the magnetic field having a direction out of a plane associated with the interface to provide a superconducting diode having a direction of current flow for which superconducting transport behavior is exhibited (page 20, section 5.2.2, and figs. 11, 11b, 11f).
Regarding claim 13, Liu also teaches wherein applying the magnetic field to the interface comprises applying the magnetic field at a predetermined magnitude and gradually reducing the magnitude of the magnetic field to zero (fig. 12b).
Regarding claim 15, Liu also shows wherein applying the one of the DC current to the interface, the out-of-plane electric field to the interface, the magnetic field to the interface, and the voltage bias to a gate electrode associated with the interface comprising applying the voltage bias to the gate to provide a superconducting diode having a direction of current flow for which superconducting transport behavior is exhibited (figs. 11, 11b, 11f).
Regarding claim 19, Liu discloses a superconducting diode assembly (fig. 11) comprising: a structure comprising a transition metal dichalcogenide layered on twisted trilayer graphene to form an interface having a stabilized time-reversal symmetry breaking field (page 1, section 1, page 14, section 4.5, figs. 2 and 8, page 21, section 5.2.3); and a control apparatus associated with the structure configured to apply a magnetic field to the interface to provide a structure that exhibits superconducting transport behavior when current flows in one direction and exhibits significant resistance when current flows in the opposite direction (page 20, section 5.2.2, fig. 11).
Regarding claim 20, Liu also teaches wherein the transition metal dichalcogenide is tungsten diselenide (page 18, section 5.2.1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7, 8, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liu and in view of US 2016/0181516 (Reed et al hereinafter Reed) .
Regarding claim 7, Liu does teach wherein the one of the first material and the second material is twisted bilayer graphene (page 9, section 4.1).
Liu does not explicitly disclose the structure is configurable via the control apparatus to store a bit within the structure.
However, this limitation is notorious old and well known.
For instance, in the related field of the invention, Reed teaches the structure is configurable via the control apparatus to store a bit within the structure; a bit state can be set using a laser pulse that changes a temperature or a charge distribution, and the bit state can be read from a resulting change in optical properties (para 93).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Reed in Liu in order to use the properties of a nano-sized material to form a memory device (Reed: para. 93, 99).
Regarding claim 8, Liu does teach wherein the one of the first material and the second material is twisted bilayer graphene (page 9, section 4.1).
Liu does not explicitly disclose the structure is configurable via the control apparatus to read a bit stored within the structure.
However, this limitation is notorious old and well known.
For instance, in the related field of the invention, Reed teaches the structure is configurable via the control apparatus to read a bit stored within the structure. The bit state of this memory cell can be measured using a conductivity or resistance difference between the semiconducting and metallic TMD sheet (para 63).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Reed in Liu in order to use the properties of a nano-sized material to form a memory device (Reed: para. 93, 99).
Regarding claim 16, as best understood 112 2nd rejection above, Liu also teaches wherein the one of the first material and the second material is twisted bilayer graphene (page 9, section 4.1).
Liu does not explicitly disclose applying the one of the DC current to the interface, the out-of-plane electric field to the interface, the magnetic field to the interface, and the voltage bias to the gate electrode associated with the interface stores a bit within the structure.
However, this limitation is notorious old and well known.
For instance, in the related field of the invention, Reed teaches applying the one of the DC current to the interface, the out-of-plane electric field to the interface, the magnetic field to the interface, and the voltage bias to the gate electrode associated with the interface stores a bit within the structure; phase transformation in TMD monolayers can be induced through the application of another stimulus or triggering mechanism in place of, or in combination with, mechanical stress or strain, such as through application of a voltage, an electrical current (para 30); a bit state can be set using a laser
pulse that changes a temperature or a charge distribution, and the bit state can be read from a resulting change in optical properties (para 93).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Reed in Liu in order to use the properties of a nano-sized material to form a memory device (Reed: para. 93, 99).
Regarding claim 17, as best understood 112 2nd rejection above, Liu does teach wherein the one of the first material and the second material is twisted bilayer graphene (page 9, section 4.1)
Liu does not explicitly disclose applying the one of the DC current to the interface, the out-of-plane electric field to the interface, the magnetic field to the interface, and the voltage bias to the gate electrode associated with the interface reads a bit stored within the structure.
However, this limitation is notorious old and well known.
For instance, in the related field of the invention, Reed teaches the bit state of this memory cell can be measured using a conductivity or resistance difference between the semiconducting and metallic TMD sheet (para 63); and phase transformation in TMD monolayers can be induced through the application of another stimulus or triggering mechanism in place of, or in combination with, mechanical stress or strain, such as through application of a voltage, an electrical current para 30).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to use the teaching by Reed in Liu in order to use the properties of a nano-sized material to form a memory device (Reed: para. 93, 99).
Allowable Subject Matter
Claims 14 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art of record fails to teach the limitations “further comprising: selecting a direction of current flow for the superconducting diode for which superconducting transport behavior is desired; selecting a direction for the magnetic field that will provide the superconducting diode with the selected direction of current flow exhibiting superconducting transport behavior; and applying the magnetic field to the interface in the selected direction to provide a superconducting diode with the selected direction of current flow exhibiting superconducting transport behavior.“ of claim 14 and the limitations “further comprising: exfoliating a surface of a first substate formed from a dielectric material to provide an atomically flat surface; applying the first material to the surface of the first substrate; exfoliating a surface of a second substrate formed from the dielectric material to provide an atomically flat surface; and applying the second material to the second substrate; wherein the first material and the second material are positioned such that the first material and the second material are substantially encapsulated by the dielectric material.“ of claim 18. Therefore, the prior art teachings neither anticipate nor render obvious the allowable subject matter in combination with the other claimed limitations.
Conclusion
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/TUAN D NGUYEN/Primary Examiner, Art Unit 2824
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