DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on applications filed in REPUBLIC OF KOREA on 12/13/2021.
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS’s) submitted on 06/11/2024, 11/18/2025 are being considered by the examiner.
Drawings
The drawings, in regards to Fig. 5, Fig.8-10, Fig. 12, Fig. 14-15, are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: {321P,521P, 721P}. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because “121” is present twice in Fig. 18 and does not match Fig. 1 in labeling. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because “according to an embodiment” is not needed and should be removed. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “CIRCUIT BOARD WITH REDUCED CAVITY SIZE”.
Claim Objections
Claims 3, 5, and 7-10 objected to because of the following informalities:
“the other side” in Claim 3 should be “an other side”
“the inner wall” in Claims 5 and 7 should be “an inner wall” or the dependency should be to Claim 2
“that” in Claim 8 can be “a thickness” to make it more clear
“an upper surface” in claim 9 should be “the upper surface”
The second “an inner wall of the cavity” in claim 10 end should be “the inner wall of the cavity”
“12” in Claim 14 should be “13”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. “a lower surface of the cavity includes a protruding surface protruding toward the outside of the cavity” is not disclosed in the specification and in the drawings.
Examiner will disregard this limitation when examining.
Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The drawings and the specification do not disclose “the metal layer includes at least one of a lower metal layer disposed between the first insulating layer and the second insulating layer and including at least a portion exposed through the cavity, and an upper metal layer disposed on the second insulating layer and including at least a portion exposed through the cavity”.
Examiner will use 421S and 460 in Fig. 7 when examining this claim.
Claim 19 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The drawings and the specification do not disclose “the protective layer includes a through hole that overlaps the cavity along a vertical direction”.
Examiner disregard that limitation when examining this claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (JP2020188059).
Regarding Claim 1. (Currently Amended) Tanaka teaches, in Fig. 1, 3-5, and 11-12, a circuit board comprising: a first insulating layer (15 2nd top); and a second insulating layer (15 1st top) disposed on an upper surface of the first insulating layer (see Fig. 4) and including a cavity (30), wherein an inner wall of the cavity includes a plurality of convex parts ( 50 - fig. 5, 56- Fig. 11-12) that are convex in a horizontal direction from an inside of the cavity to an outside of the cavity (see Fig. 3).
Regarding Claim 2. (Original) Tanaka teaches the circuit board of claim 1, further comprising: a first through electrode(18 2nd top to bottom) passing through the first insulating layer; and a second through electrode (18 1st top) passing through the second insulating layer, wherein an inclination angle of an inner wall (30A) of the cavity corresponds to an inclination angle of a side surface of the second through electrode (implicit, see Fig. 4).
Regarding Claim 3. (Original) Tanaka teaches, in Fig. 4, the circuit board of claim 2, wherein the inner wall of the cavity includes: a first inner wall (30A) positioned at one side of the cavity (30), and a second inner wall (other side 30A) positioned at the other side of the cavity (see Fig. 4) and facing the first inner wall (see Fig. 4), wherein the second through electrode (18-top) includes: a first side surface (left side) positioned at one side of the second through electrode, and a second side surface (right side) positioned at the other side of the second through electrode opposite to the first side surface, wherein an inclination angle of the first inner wall of the cavity corresponds to an inclination angle of the first side surface of the second through electrode (implicit, see Fig .4), and wherein an inclination angle of the second inner wall of the cavity corresponds to an inclination angle of the second side surface of the second through electrode (implicit, see Fig. 4).
Regarding Claim 4. (Original) Tanaka teaches the circuit board of claim 3, wherein the inclination angle of the first inner wall (30A) is an internal angle between a lower surface of the cavity and the first inner wall (see Fig. 4), wherein the inclination angle of the second inner wall is an internal angle between the lover surface of the cavity and the second inner wall (see Fig. 4), wherein the inclination angle of the first side surface of the second through electrode is an internal angle between a lower surface of the second through electrode and the first side surface (see Fig. 4), and wherein the inclination angle of the second side surface of the second through electrode is an internal angle between the lower surface of the second through electrode and the second side surface (see Fig. 4), and wherein the inclination angle of each of the first inner wall, the second inner wall, the first side surface, and the second side surface satisfies a range of 91 to 115 degrees (implicit, Fig .4, angle beyond 90 degrees)).
Regarding Claim 6. (Original) Tanaka teaches the circuit board of claim 1, further comprising: a first circuit pattern layer (16, 36) disposed between an upper surface of the first insulating layer and a lower surface of the second insulating layer, wherein the first circuit pattern layer includes a first pad (36) disposed in a first region of the first insulating layer vertically overlapping a lower surface of the cavity (see Fig .4).
Regarding Claim 12. (New) Tanaka teaches, in Fig. 5, 11-12, the circuit board of claim 2, wherein a radius of curvature of the convex part (D0, D1) corresponds to a radius of curvature of an upper surface of the second through electrode (implicit, as the internal angle match, the radius of curvature should correspond to a radius of curvature).
Claim(s) 1, 13-15, and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katsura (JP4925905).
Regarding Claim 1. (Currently Amended) Katsura teaches, in Fig. 6-8, a circuit board comprising: a first insulating layer (60’); and a second insulating layer (60) disposed on an upper surface of the first insulating layer (see Fig. 8) and including a cavity (24), wherein an inner wall of the cavity (see Fig. 8) includes a plurality of convex parts (60, 62 ,Fig. 6-7) that are convex in a horizontal direction from an inside of the cavity to an outside of the cavity (see Fig. 6-7).
Regarding Claim 1. (Currently Amended) Katsura teaches, in Fig. 6-8, a circuit board comprising: a first insulating layer (60’); and a second insulating layer (60 third from top) disposed on an upper surface of the first insulating layer (see Fig. 8) and including a cavity (24), wherein an inner wall of the cavity (see Fig. 8) includes a plurality of convex parts (60, 62 ,Fig. 6-7) that are convex in a horizontal direction from an inside of the cavity to an outside of the cavity (see Fig. 6-7).
Regarding Claim 13. (New) Katsura teaches the circuit board of claim 1, further comprising: a third insulating layer (60 2nd from top) disposed on the second insulating layer (60 third from top- Fig. 8), wherein the cavity includes: a first part (24 bottom) formed in the second insulating layer; and a second part (24 second to bottom) formed in the third insulating layer and connected to the first part.(see Fig. 8)
Regarding Claim 14. (New) Katsura teaches the circuit board of claim 13, wherein the inner wall of the cavity includes a first inner wall (27A) provided in the second insulating layer, and a second inner wall (26A) provided in the third insulating layer, and wherein the first inner wall and the second inner wall have a step (see Fig. 8).
Regarding Claim 15. (New) Katsura teaches the circuit board of claim 14, wherein a horizontal width of the first part of the cavity in a region closest to the third insulating layer is greater than a horizontal width of the second part of the cavity in a region closest to the second insulating layer (see Fig. 8, seems similar to Fig. 6 of application).
Regarding Claim 17. (New) Katsura teaches the circuit board of claim 1, further comprising: an electronic device (3) disposed in the cavity, and wherein the electronic device overlaps the convex part along the horizontal direction (see Fig. 8).
Regarding Claim 18. (New) Katsura teaches the circuit board of claim 17, further comprising: a burying insulating layer (24A- Fig. 8(C)) disposed in the cavity and burying the electronic device, and wherein the burying insulating layer has a concave part corresponding to the convex part (see Fig. 8 is similar to Fig. 18 of application).
Regarding Claim 19. (New) Katsura teaches the circuit board of claim 1, further comprising: a protective layer (60”) disposed on the second insulating layer (60).
Regarding Claim 20. (New) Katsura teaches the circuit board of claim 1, wherein the plurality of convex parts are connected to each other in a circumferential direction of the lower surface of the cavity (see Fig. 6-7).
Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noda (US9723729).
Regarding Claim 1. (Currently Amended) Noda teaches, in Fig. 1, 2A-2B, 7A-7E, a circuit board comprising: a first insulating layer (55F); and a second insulating layer (30) disposed on an upper surface of the first insulating layer and including a cavity (70F), and wherein an inner wall of the cavity includes a plurality of convex parts (34FI) that are convex in a horizontal direction from an inside of the cavity to an outside of the cavity (See Fig. 7C-7E).
Regarding Claim 10. (Original) Noda teaches the circuit board of claim 1, wherein the second insulating layer includes a recessed part (55Ff, 55Fw) formed at an inner wall of the cavity adjacent to an upper surface of the first insulating layer and concave in the inner direction of the second insulating layer (see Fig. 2A-2B), and wherein at least a portion of the recessed part vertically overlaps an inner wall of the cavity (see Fig. 2A-2B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Claim(s) 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Atsuo (WO2021059416).
Regarding Claim 7. Tanaka teaches the circuit board of claim 6, but does not teach wherein the first circuit pattern layer includes a second pad spaced apart from the first pad and vertically overlapping the inner wall of the cavity.
Atsuo teaches the first circuit pattern layer (80,17, 12) includes a second pad (12) spaced apart from the first pad (80,17) and vertically overlapping the inner wall of the cavity (see Fig. 13)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit pattern as disclosed by Tanaka with the second pad as disclosed by Atsuo in order to act as shielding member to laser light (Atsuo, page 8 paragraph 7) and easier to manufacture by requiring less different material as it is known in the art.
Regarding Claim 8. (Original) Tanaka and Atsuo teaches the circuit board of claim 7, wherein a thickness of the first pad is greater than that of the second pad (Atsuo, Fig .13).
Regarding Claim 9. (Original) Tanaka and Atsuo teaches the circuit board of claim 7, wherein the first circuit pattern layer includes a first metal layer ( Atsuo- 12, 17) disposed on an upper surface of the first insulating layer, and a second metal layer (80- Atsuo) disposed on the first metal layer, wherein the first pad includes both the first and second metal layers (see Atsuo, Fig. 13), and wherein the second pad includes only the first metal layer (see Atsuo Fig. 13).
Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of White (US2006017152).
Regarding Claim 5. (Original) Tanaka teaches, the circuit board of claim 1, but does not teach a metal layer disposed on at least a part of the inner wall of the cavity.
White teaches, Fig. 6B, a metal layer (640, 642) disposed on at least a part of the inner wall of the cavity (630).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cavity as disclosed by Tanaka with the metal layer as disclosed by White in order to reduce interconnect lengths and metal shielding (White, [0007], [0051]).
Regarding Claim 11. (New) Tanaka and White teaches the circuit board of claim 5, wherein the metal layer includes at least one of a lower metal layer (640, 642 bottom layer) disposed between the first insulating layer (602,622, 610)) and the second insulating layer (620, 616) and including at least a portion (640, 642 middle layer) exposed through the cavity, and an upper metal layer (640, 642 top layer) disposed on the second insulating layer and including at least a portion (640, 642 middle layer) exposed through the cavity (Fig. 6B).
Claim(s) 5 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Kang (US2019/198429).
Regarding Claim 5. (Original) Tanaka teaches the circuit board of claim 1, but does not teach a metal layer disposed on at least a part of the inner wall of the cavity.
KANG teaches, in Fig. 15, a metal layer (126, 127, 129) disposed on at least a part of the inner wall of the cavity (110H).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the cavity as disclosed by Tanaka with the metal layer on the inner wall as disclosed by KANG in order to block electromagnetic waves (KANG, [0075]) .
Regarding Claim 11. (New) Tanaka and KANG teaches the circuit board of claim 5, wherein the metal layer includes at least one of a lower metal layer (126) disposed between the first insulating layer (111b) and the second insulating layer (111a) and including at least a portion (127 top area) exposed through the cavity, and an upper metal layer (129) disposed on the second insulating layer and including at least a portion exposed through the cavity (127 bottom area).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and Atsuo in view of 차상석 (KR102102322).
Regarding Claim 16. (New) Tanaka and Atsuo does the circuit board of claim 7, but does not teach the first circuit pattern layer further includes: a third pad that does not overlap the cavity along a vertical direction; and a connection pattern layer connecting the first pad and the third pad and including a first portion that overlaps the cavity along the vertical direction and a second portion that does not overlap the cavity along the vertical direction.
차상석 teaches, in Fig. 14, the first circuit pattern layer further includes: a third pad (142) that does not overlap the cavity along a vertical direction (see Fig. 14); and a connection pattern layer (150) connecting the first pad (122) and the third pad (142) and including a first portion (middle portion of 150) that overlaps the cavity along the vertical direction (see Fig. 14) and a second portion (top portion of 150) that does not overlap the cavity along the vertical direction (see Fig. 14).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit board as disclosed by Tanaka and Atsuo with the first circuit pattern layer as disclosed by 차상석 in order to improve high-speed operation and heat dissipation performance by improving the performance (차상석, page 4 paragraph 10) .
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is presented in the Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMED AZAM whose telephone number is (571)270-0593. The examiner can normally be reached Mon-Fri 11:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MA/Examiner, Art Unit 2848
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2848