DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by EP2034550.
Regarding claim 7, EP2034550’s figure 1 shows A phase adjustment circuit comprising: a clock generator configured to generate a sinusoidal clock signal (E); a delay circuit (1)configured to delay a signal output from the clock generator; a first multiplier (3) configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant (gain A); a second multiplier (2) configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant (B); and an adder (S) configured to add the signal output from the first multiplier and the signal output from the second multiplier (S = AE + BE’) as called for in claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 in view of Nagatani et al. (USP 10,243,664).
Regarding claims 8, EP2034550’s figure 1 shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for the first multiplier circuit as called for in claim 8.
Nagatani et al.’s figures 15-17 shows a current source comprises a transistor and a resistor, and figure 28 shows a Gilbert multiplier circuit comprises transistors, resistor and a current source (IS40) that can be constructed as the current source shown in figure 15-17. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Nagatani et al.’s Gilbert multiplier circuits in EP2034550’s circuit arrangement because Gilbert multiplier circuit cell has high speed response as taught by Nagatani et al. reference.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and Nagatani et al. (USP 10,243,664) and in further view of Simmons (USP 4,806,792).
Regarding claim 9, the combination of EP2034550 and Nagatani references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for the details of the adder as called for in claim 9.
Simmons’s figure 1 shows an adder comprising transistors (11a, 12a, 11b, 12b, 15a, 15b) resistors 23, 24, 17a, 17b, 18a, 18b, 16a, 16b) for adding input signals. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention was made to include Simmon’s adder in EP2034550’s circuit arrangement for the purpose of obtaining a high speed response as taught by Simmon reference.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and Nagatani et al. (USP 10,243,664) and further in view of Parkinson (USP 5,210,450).
Regarding claim 10, the combination of EP2034550 and Nagatani et al. references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a plurality of delay circuits with different delay amounts and a switch inserted between the plurality of delay circuits and the second multiplier as called for in claim 10.
Parkinson’s figure 4 shows a variable delay circuit comprising a plurality of delay circuits (0, 1, 2, 3) with different delay amounts and a switch (20) inserted between the plurality of delay circuits for selecting different delay time. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace EP2034550’s delay circuit (1) with Parkinson’s variable delay circuit for the purpose of providing different delay time as desired as taught by Parkinson reference.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and Nagatani et al. (USP 10,243,664) and further in view of JP 2004-096232A.
Regarding claim 11, the combination of EP2034550 and Nagatani references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder as called for in claim 11.
JP2004-096232A’s figures 6-7 shows a variable attenuator (R5) for power adjustment as the output of an adder to preserve the output signal integrity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include JP 2004-096232A’s variable attenuator in EP2034550’s circuit arrangement for the purpose of preserving signal integrity as taught by JP 2004-096232A’s reference.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 in view of Simmons (USP 4,806,792).
Regarding claim 12, the EP2034550 reference shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for the details of the adder as called for in claim 12.
Simmons’s figure 1 shows an adder comprising transistors (11a, 12a, 11b, 12b, 15a, 15b) resistors 23, 24, 17a, 17b, 18a, 18b, 16a, 16b) for adding input signals. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention was made to include Simmon’s adder in EP2034550’s circuit arrangement for the purpose of obtaining a high speed response as taught by Simmon reference.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and Simmons (USP 4,806,792) further in view of Parkinson (USP 5,210,450).
The combination of EP2034550 and Simmons reference shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a plurality of delay circuits with different delay amounts and a switch inserted between the plurality of delay circuits and the second multiplier as called for in claim 13.
Parkinson’s figure 4 shows a variable delay circuit comprising a plurality of delay circuits (0, 1, 2, 3) with different delay amounts and a switch (20) inserted between the plurality of delay circuits for selecting different delay time. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace EP2034550’s delay circuit (1) with Parkinson’s variable delay circuit for the purpose of providing different delay time as desired as taught by Parkinson reference.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and Simmons (USP 4,806,792) and further in view of JP 2004-096232A.
Regarding claim 14, the combination of EP2034550 and Simmons references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder as called for in claim 14.
JP2004-096232A’s figures 6-7 shows a variable attenuator (R5) for power adjustment as the output of an adder to preserve the output signal integrity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include JP 2004-096232A’s variable attenuator in EP2034550’s circuit arrangement for the purpose of preserving signal integrity as taught by JP 2004-096232A’s reference.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and in view of Parkinson (USP 5,210,450).
The EP2034550 reference shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a plurality of delay circuits with different delay amounts and a switch inserted between the plurality of delay circuits and the second multiplier as called for in claim 15.
Parkinson’s figure 4 shows a variable delay circuit comprising a plurality of delay circuits (0, 1, 2, 3) with different delay amounts and a switch (20) inserted between the plurality of delay circuits for selecting different delay time. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace EP2034550’s delay circuit (1) with Parkinson’s variable delay circuit for the purpose of providing different delay time as desired as taught by Parkinson reference.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and Parkinson (USP 5,210,450) and further in view of JP 2004-096232A.
Regarding claim 16, the combination of EP2034550 and Parkinson references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder as called for in claim 16.
JP2004-096232A’s figures 6-7 shows a variable attenuator (R5) for power adjustment as the output of an adder to preserve the output signal integrity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include JP 2004-096232A’s variable attenuator in EP2034550’s circuit arrangement for the purpose of preserving signal integrity as taught by JP 2004-096232A’s reference.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and in view of JP 2004-096232A.
Regarding claim 17, the EP2034550 reference shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder as called for in claim 16.
JP2004-096232A’s figures 6-7 shows a variable attenuator (R5) for power adjustment as the output of an adder to preserve the output signal integrity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include JP 2004-096232A’s variable attenuator in EP2034550’s circuit arrangement for the purpose of preserving signal integrity as taught by JP 2004-096232A’s reference.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and in view of Nagatani et al. (USP 10,243,664) and Simmons (USP 4,806,792).
Regarding claim 18, EP2034550’s figure 1 shows A phase adjustment circuit comprising: a clock generator configured to generate a sinusoidal clock signal ( E ); a delay circuit (1) configured to delay a signal output from the clock generator; and a process circuit including: a first multiplier (3) configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant (A); a second multiplier (2) configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant (B); and an adder configured to add (S) the signal output from the first multiplier and the signal output from the second multiplier.
EP2034550 does not show the details of the multiplier and the adder comprising the transistors and resistors as called for in claim 18.
Nagatani et al.’s figures 15-17 shows a current source comprises a transistor and a resistor, and figure 28 shows a Gilbert multiplier circuit comprises transistors, resistor and a current source (IS40) that can be constructed as the current source shown in figure 15-17. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Nagatani et al.’s Gilbert multiplier circuits in EP2034550’s circuit arrangement because Gilbert multiplier circuit cell has high speed response as taught by Nagatani et al. reference.
Simmons’s figure 1 shows an adder comprising transistors (11a, 12a, 11b, 12b, 15a, 15b) resistors 23, 24, 17a, 17b, 18a, 18b, 16a, 16b) for adding input signals. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention was made to include Simmon’s adder in EP2034550’s circuit arrangement for the purpose of obtaining a high speed response as taught by Simmon reference.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550, Nagatani et al. (USP 10,243,664) and Simmons (USP 4,806,792) and further in view Parkinson (USP 5,210,450).
The combination of EP2034550, Nagatani et al. and Simmons references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a plurality of delay circuits with different delay amounts and a switch inserted between the plurality of delay circuits and the second multiplier as called for in claim 19.
Parkinson’s figure 4 shows a variable delay circuit comprising a plurality of delay circuits (0, 1, 2, 3) with different delay amounts and a switch (20) inserted between the plurality of delay circuits for selecting different delay time. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace EP2034550’s delay circuit (1) with Parkinson’s variable delay circuit for the purpose of providing different delay time as desired as taught by Parkinson reference.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550, Nagatani et al. (USP 10,243,664) and Simmons (USP 4,806,792) and further in view JP 2004-096232A.
Regarding claim 20, the combination of EP2034550, Nagatani et al. and Simmons references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder as called for in claim 16.
JP2004-096232A’s figures 6-7 shows a variable attenuator (R5) for power adjustment as the output of an adder to preserve the output signal integrity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include JP 2004-096232A’s variable attenuator in EP2034550’s circuit arrangement for the purpose of preserving signal integrity as taught by JP 2004-096232A’s reference.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2842 2/2/2026