DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 4/22/2026. Claims 18-20 are pending and are under examination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. In this instant, the specification has failed to describe as to a circuit output represented by (OUT2p-OUT2n) is a voltage obtained by adding the square of (IN1p-IN1n) and the square of (IN3p-IN3n) at the time the application was filed. As presently claimed in claim 18, the adder is configured to add the signal output from the first multiplier and the signal output from the second multiplier. Multiplier is the output of a signal and a constant. It is different from a square of a signal as claimed. Clarification and correction are required.
Claims 19-20 are also rejected under 35USC 112, first paragraph because of the technical deficiencies of claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550 and in view of Nagatani et al. (USP 10,243,664) and Simmons (USP 4,806,792).
Regarding claim 18, EP2034550’s figure 1 shows A phase adjustment circuit comprising: a clock generator configured to generate a sinusoidal clock signal ( E ); a delay circuit (1) configured to delay a signal output from the clock generator; and a process circuit including: a first multiplier (3) configured to output a signal obtained by multiplying an amplitude of the signal output from the clock generator by a first constant (A); a second multiplier (2) configured to output a signal obtained by multiplying an amplitude of the signal output from the delay circuit by a second constant (B); and an adder configured to add (S) the signal output from the first multiplier and the signal output from the second multiplier.
EP2034550 does not show the details of the multiplier and the adder comprising the transistors and resistors as called for in claim 18.
Nagatani et al.’s figures 15-17 shows a current source comprises a transistor and a resistor, and figure 28 shows a Gilbert multiplier circuit comprises transistors (first transistor Q41, second transistor Q40, third transistor Q42, fourth transistor Q42, fifth transistor Q44, sixth transistor Q45, seventh transistor Q22 (figure 17) represents the current source IS40), resistors (first resistor R4, second resistor R40, third resistor R46, fourth resistor R47, fifth resistor R24 of figure 17 which represents the current source IS40, and a current source (IS40) that can be constructed as the current source shown in figure 15-17. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Nagatani et al.’s Gilbert multiplier circuits in EP2034550’s circuit arrangement because Gilbert multiplier circuit cell has high speed response as taught by Nagatani et al. reference.
Regarding the details of the adder, Simmons’s figure 1 shows an adder comprising transistors (eighth transistor 12a, ninth transistor 12b, tenth transistor 11a, eleventh transistor 11b, twelfth transistor 15a, thirteenth transistor 15b, fourth transistor (Q22 of Nagatani’s figure 15 which represents -Vc); and resistors (sixth resistor 16A, seventh resistor 16B, eighth resistor R24 of Nagatani’s figure 15 which represents -Vc) for adding input signals. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention was made to include Simmon’s adder in EP2034550’s circuit arrangement for the purpose of obtaining a high speed response as taught by Simmon reference.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550, Nagatani et al. (USP 10,243,664) and Simmons (USP 4,806,792) and further in view Parkinson (USP 5,210,450).
The combination of EP2034550, Nagatani et al. and Simmons references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a plurality of delay circuits with different delay amounts and a switch inserted between the plurality of delay circuits and the second multiplier as called for in claim 19.
Parkinson’s figure 4 shows a variable delay circuit comprising a plurality of delay circuits (0, 1, 2, 3) with different delay amounts and a switch (20) inserted between the plurality of delay circuits for selecting different delay time. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to replace EP2034550’s delay circuit (1) with Parkinson’s variable delay circuit for the purpose of providing different delay time as desired as taught by Parkinson reference.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by EP2034550, Nagatani et al. (USP 10,243,664) and Simmons (USP 4,806,792) and further in view JP 2004-096232A.
Regarding claim 20, the combination of EP2034550, Nagatani et al. and Simmons references shows a phase adjustment circuit comprising all the aspects of the present invention as noted above except for a level adjusting circuit configured to perform an amplitude adjustment of the signal output from the adder as called for in claim 16.
JP2004-096232A’s figures 6-7 shows a variable attenuator (R5) for power adjustment as the output of an adder to preserve the output signal integrity. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to include JP 2004-096232A’s variable attenuator in EP2034550’s circuit arrangement for the purpose of preserving signal integrity as taught by JP 2004-096232A’s reference.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
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/TUAN T LAM/Primary Examiner, Art Unit 2836 5/30/2026
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