Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (Claims 1-15, 21 and 30) in the reply filed on 07/28/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claims 27-28 and 31 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Group II and Group III.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-11 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Cho (US 2015/0243724) in view of Son (US 2023/0282173).
Regarding claim 1, Cho teaches a display substrate (Fig. 1A-2 and Fig. 7, [0032-0078]), comprising:
a base substrate (SUB in Fig. 1A-1B, [0033, 0040-0041]);
a plurality of sub-pixels ([0033-0034], a plurality of pixel area is arrayed in a matrix manner in the display area, Fig. 7) disposed on the base substrate (SUB in Fig. 1A-1B, [0033, 0040-0041]), wherein the plurality of sub-pixels ([0033-0034], a plurality of pixel area is arrayed in a matrix manner in the display area, Fig. 7) are arranged in an array along a first direction and a second direction on the base substrate ([0033-0034], Fig. 7), and at least one sub-pixel of the plurality of sub-pixels comprises a first electrode ([0055], the pixel electrode connected to drain electrode D1 and/or D2);
a first transistor (T2 in Fig. 1B) and a second transistor (T1 in Fig. 1B) which are disposed on the base substrate (SUB in Fig. 1A-1B, [0033, 0040-0041]), wherein the first transistor (T2 in Fig. 1B) comprises an active layer (the layer corresponding to A2 in Fig. 1B, [0053, 0146]) and a gate (G2 in Fig. 1B), the active layer (the layer corresponding to A2 in Fig. 1B, [0053, 0146]) of the first transistor comprises a channel region (the middle region of A2 in Fig. 1B), a first electrode region and a second electrode region (the regions corresponding to the two edge portions of A2 in Fig. 1B), and the second transistor (T1 in Fig. 1B) comprises an active layer (the layer corresponding to A1 in Fig. 1B), a gate (G1 in Fig. 1B), a first electrode and a second electrode (S1 and D1 in Fig. 1B); and
a data line (DL in Fig. 1B) disposed on the base substrate (SUB in Fig. 1A-1B, [0033, 0040-0041]), wherein the data line (DL in Fig. 1B and 7-8, [0059, 0062, 0129]) extends in the second direction (the vertical direction in Fig. 7-8) on the base substrate (Fig. 1B and 7-8), wherein the display substrate comprises:
a first semiconductor layer (A1 in Fig. 1A-1B) located on the base substrate (SUB in Fig. 1A-1B);
a first conductive layer (the layer corresponding to G1 and GL in Fig. 1A-1B) located on a side of the first semiconductor layer away from the base substrate (Fig. 1A-1B);
a second conductive layer (the layer corresponding to DL, G2, S1 and D1 in Fig. 1A-1B) located on a side of the first conductive layer away from the base substrate (Fig. 1A-1B);
a second semiconductor layer (A2 in Fig. 1A-1B) located on a side of the second conductive layer away from the base substrate (Fig. 1A-1B);
a third conductive layer (the layer corresponding to D1 and S2 in Fig. 1A-1B) located on a side of the second semiconductor layer away from the base substrate (Fig. 1A-1B); and
a fourth conductive layer ([0055], the layer corresponding to the pixel electrode connected to drain electrode D2) located on the third conductive layer ([0055]);
wherein the active layer (the layer corresponding to A1 in Fig. 1B, [0053, 0146]) of the second transistor is located in the first semiconductor layer (A1 in Fig. 1A-1B), the gate (G1 in Fig. 1B) of the second transistor is located in the first conductive layer (the layer corresponding to G1 and GL in Fig. 1A-1B), and the first electrode of the second transistor and the second electrode of the second transistor (S1 and D1 in Fig. 1B) are located in the second conductive layer (the layer corresponding to DL, G2, S1 and D1 in Fig. 1A-1B); the active layer (the layer corresponding to A2 in Fig. 1B, [0053, 0146]) of the first transistor is located in the second semiconductor layer (A2 in Fig. 1A-1B), and the first electrode ([0055], the pixel electrode connected to drain electrode D1 and/or D2) of the at least one sub-pixel is located in the fourth conductive layer ([0055], the layer corresponding to the pixel electrode connected to drain electrode D2); and
wherein the data line (DL in Fig. 1B) is located in one of the first conductive layer and the second conductive layer (the layer corresponding to DL, G2, S1 and D1 in Fig. 1A-1B), the first electrode region (the region corresponding to S2 and A2 in Fig. 1B) of the active layer of the first transistor (T2 in Fig. 1B) is electrically connected to the data line (Fig. 1B), and the first electrode ([0055], the pixel electrode connected to drain electrode D1 and/or D2) of the at least one sub-pixel is electrically connected to the second electrode region (the region corresponding to A2 and D2 in Fig. 1B) of the active layer of the first transistor (T2 in Fig. 1B).
Cho does not teach that the fourth conductive layer located on a side of the third conductive layer away from the base substrate; and the gate of the first transistor is located in the third conductive layer.
Son teaches that (Fig. 1-2 and 15, [0081, 0088, 0093, 0093]) a fourth conductive layer (the layer corresponding to RME1 in Fig. 2 and 15, [0097]) located on a side of a third conductive layer (the layer corresponding to GE in Fig. 2 and 15, [0093]) away from the base substrate (SUB1 in Fig. 2 and 15); and a gate (GE in Fig. 2 and 15, [0093]) of a first transistor (the transistor corresponding to ACT, GE, SE and DE in Fig. 2 and 15) is located in the third conductive layer ([0093]).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Son for the system of Cho such that in the system of Cho, the fourth conductive layer located on a side of the third conductive layer away from the base substrate; and the gate of the first transistor is located in the third conductive layer. The motivation is that an area of the non-display area NDA may be minimized (Son, [0081]).
Regarding claims 10-11 and 30, Cho also teaches the following elements:
(Claim 10) the first electrode region (the region corresponding to S2 and A2 in Fig. 1B) of the active layer (A2 in Fig. 1B) of the first transistor (T2 in Fig. 1B) is electrically connected to the data line (DL in Fig. 1B) through a lap joint portion (Fig. 1B).
(Claim 11) the lap joint portion (Fig. 1B) is located in the third conductive layer (Fig. 1B).
(Claim 30) A display device ((Fig. 1A-2 and Fig. 7, [0005-0008, 0032-0078])) comprising the display substrate (Fig. 1A-2 and Fig. 7, [0032-0078]).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Son as applied to claim 1 above, and further in view of Lee (KR102390472B1)
Regarding claim 2, Cho teaches that the display substrate further comprises a light shielding portion ([0042]). Cho does not teach the following elements.
Lee teaches the following elements (Fig. 3, Pages 7-10 of English translation of KR102390472B1):
(Claim 2) an orthographic projection of a light shielding portion (GB in Fig. 3, Pages 7-8) on a base substrate at least partially overlaps (Fig. 3) with the channel region of the active layer (A2 in Fig. 3) of the first transistor (T2 in Fig. 3), and the light shielding portion (GB in Fig. 3, Pages 7-8) is located in one of a first conductive layer (the layer corresponding to G1 and GB in Fig. 3) and a second conductive layer.
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Lee for the system of Cho in view of Son such that in the system of Cho in view of Son,
(Claim 2) an orthographic projection of the light shielding portion on the base substrate at least partially overlaps with the channel region of the active layer of the first transistor, and the light shielding portion is located in one of the first conductive layer and the second conductive layer.
The motivation is that a problem such as current leakage due to external light is prevented, and it is possible to solve the problem that the characteristics of the second thin film transistor T2 change due to an external environment or the like (Lee, Page 8, Paragraph 2-3).
Regarding claim 3, Cho teaches that the data line (DL in Fig. 1B) and the second gate (G1 in Fig. 1B) are located in different conductive layers (Fig. 1B). Cho does not teach the following elements.
Lee teaches the following elements (Fig. 3, Pages 7-10 of English translation of KR102390472B1):
(Claim 3) the light shielding portion (GB in Fig. 3, Pages 7-8) and the second gate (G1 in Fig. 3) are located in same conductive layers (Fig. 3).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Lee for the system of Cho in view of Son and Lee such that in the system of Cho in view of Son and Lee,
(Claim 3) the light shielding portion and the second gate are located in same conductive layers; therefore, the data line and the light shielding portion are located in different conductive layers.
The motivation is that a problem such as current leakage due to external light is prevented, and it is possible to solve the problem that the characteristics of the second thin film transistor T2 change due to an external environment or the like (Lee, Page 8, Paragraph 2-3).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Son and Lee as applied to claim 2 above, and further in view of Sun (US 2015/0311232)
Regarding claim 6, Cho does not teach the following elements.
Sun teaches the following elements (Fig. 12-13, [0075, 0092-0093, 0097]):
(Claim 6) a data line (107 in Fig. 12-13) and a light shielding portion (116 in Fig. 12-13) are located in a same conductive layer (Fig. 12-13).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Sun for the system of Cho in view of Son and Lee such that in the system of Cho in view of Son and Lee,
(Claim 6) the data line and the light shielding portion are located in a same conductive layer.
The motivation is that the leakage current of the thin film transistor may be reduced, and/or and the manufacturing cost is reduced (Sun, [0093, 0097]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Son as applied to claim 1 above, and further in view of Yamaguchi (US 2006/0192204)
Regarding claim 13, Cho does not teach the following elements.
Yamaguchi teaches the following elements (Fig. 2A, [0020, 0005]):
(Claim 13) a lap joint portion (the portion corresponding to 16 in Fig. 2A) comprises a transparent conductive material ([0020, 0005]).
Before the effective filling date of the claimed invention, it would have been obvious to the artisan of ordinary skill to employ the above elements as taught by Yamaguchi for the system of Cho in view of Son such that in the system of Cho in view of Son,
(Claim 13) the lap joint portion comprises a transparent conductive material.
The motivation is to have a larger opening ratio thereof (Yamaguchi, [0004]).
Allowable Subject Matter
Claims 4-5, 7-9, 12, 14-15 and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
None of the prior art of record discloses or suggests all the combination of a display substrate as set forth in claims 4-5, 7-9, 12, 14-15 and 21.
Regarding claims 4-5, none of the prior art discloses or suggests a display substrate recited in claim 3, wherein “the data line and the light shielding portion are located in different conductive layers, and the orthographic projection of the light shielding portion on the base substrate partially overlaps with an orthographic projection of the data line on the base substrate” in combination with the other required elements of the claim.
Regarding claim 7, none of the prior art discloses or suggests a display substrate recited in claim 6, wherein “the data line and the light shielding portion are located in a same conductive layer, the light shielding portion is connected to the data line, and the light shielding portion protrudes along the first direction from the data line” in combination with the other required elements of the claim.
Regarding claims 8-9, none of the prior art discloses or suggests a display substrate recited in claim 6, wherein “the display substrate further comprises a dummy data line disposed on the base substrate, the dummy data line extends along the second direction on the base substrate, and the data line and the dummy data line are alternately disposed in the first direction; and the light shielding portion is connected to the dummy data line, and the light shielding portion protrudes along the first direction from the dummy data line” in combination with the other required elements of the claim.
Regarding claim 12, none of the prior art discloses or suggests a display substrate recited in claim 11, wherein “the display substrate further comprises a gate line disposed on the base substrate, the gate line extends in the first direction, and an orthographic projection of a part of the gate line on the base substrate overlaps with an orthographic projection of the active layer of the first transistor on the base substrate, so as to form the gate of the first transistor; and an orthographic projection of the lap joint portion on the base substrate and an orthographic projection of the gate line on the base substrate are spaced apart from each other in the second direction” in combination with the other required elements of the claim.
Regarding claim 14, none of the prior art discloses or suggests a display substrate recited in claim 1, wherein “the display substrate comprises: a first insulation layer disposed between the second semiconductor layer and the fourth conductive layer; and a first via hole passing through the first insulation layer; and the first electrode of the sub-pixel is electrically connected to the second electrode region of the active layer of the first transistor through the first via hole; the first electrode region of the active layer of the first transistor is electrically connected to the data line through a lap joint portion; and the lap joint portion and the first electrode of the at least one sub-pixel are located in the fourth conductive layer, and the first electrode of the at least one sub- pixel comprises a transparent conductive material” in combination with the other required elements of the claim.
Regarding claim 15, none of the prior art discloses or suggests a display substrate recited in claim 1, wherein the display substrate comprises: a fifth conductive layer disposed between the third conductive layer and the fourth conductive layer; and a conductive transfer portion located in the fifth conductive layer; and the first electrode of the at least one sub-pixel is electrically connected to the second electrode region of the active layer of the first transistor through the conductive transfer portion; and wherein “the display substrate further comprises: a first sub-insulation layer disposed between the second semiconductor layer and the fifth conductive layer; a second sub-insulation layer disposed between the fifth conductive layer and the fourth conductive layer; a second via hole passing through the first sub-insulation layer; and a third via hole passing through the second sub-insulation layer; the first electrode of the at least one sub-pixel is electrically connected to the second electrode region of the active layer of the first transistor through the third via hole, the conductive transfer portion and the second via hole; an orthographic projection of the third via hole on the base substrate falls within the orthographic projection of the light shielding portion on the base substrate; the orthographic projection of the second via hole on the base substrate and the orthographic projection of the third via hole on the base substrate are spaced apart from each other; the first electrode region of the active layer of the first transistor is electrically connected to the data line through a lap joint portion; the lap joint portion and the conductive transfer portion are located in the fifth conductive layer; and the lap joint portion and the first electrode of the at least one sub-pixel are located in the fourth conductive layer” in combination with the other required elements of the claim.
Regarding claim 21, none of the prior art discloses or suggests a display substrate recited in claim 1, wherein “a second insulation layer located between a conductive layer in which the data line is located and the second semiconductor layer; and a fourth via hole passing through the second insulation layer; and the first electrode region of the active layer of the first transistor is directly in contact with the data line through the fourth via hole; the display substrate further comprises a gate line disposed on the base substrate, the gate line extends in the first direction, and an orthographic projection of a part of the gate line on the base substrate overlaps with an orthographic projection of the active layer of the first transistor on the base substrate; an orthographic projection of the fourth via hole on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate; the active layer of the first transistor comprises a metal oxide semiconductor material; and/or, the active layer of the second transistor comprises a low temperature poly-silicon semiconductor material; and the at least one sub-pixel further comprises a second electrode, the first electrode of the at least one sub-pixel is one of a pixel electrode or a common electrode, and the second electrode of the at least one sub-pixel is the other of the pixel electrode or the common electrode” in combination with the other required elements of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAN LIU whose telephone number is (571)270-0383. The examiner can normally be reached on 9am-5pm EST M-F.
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/Shan Liu/
Primary Examiner, Art Unit 2871
Prosecution Insights