DETAILED ACTION
This office action is in response to claims filed on 06/12/2024. Claims 1-15 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/12/2024 was filed after the filing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 recites the limitation "the power conversion device". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kempitiya US 10,680,601 B1 (Hereinafter “Kempitiya”).
Regarding Claim 1, Kempitiya teaches a drive circuit controls switching time of a voltage-driven switching element (Fig. 6, 600), the drive circuit (Fig. 6, 606) comprising:
the voltage-driven switching element (Fig. 6, 602);
an on-circuit (Fig. 6, 620) that injects a charge into a gate of the voltage-driven switching element in response to a drive signal; and
an off-circuit (Fig. 6, 624) that extracts the charge from the gate of the voltage-driven switching element in response to a drive signal,
wherein the injection of the charge into the gate of the voltage-driven switching element or the extraction of the charge from the gate by pulse driving of the on- circuit or the off-circuit, and switching time of the voltage-driven switching element is controlled (Fig. 6, 604).
Regarding Claim 5, Kempitiya teaches the drive circuit according to claim 4, wherein the drive circuit is used in a circuit that generates an alternating current having a number of phases of at least three phases (Col. 5, lines 36-43).
Regarding Claim 12, Kempitiya teaches the drive circuit according to claim 1, wherein the voltage-driven switching element mounted on the power conversion device is driven and controlled (Col. 8, Lines 3-14).
Regarding Claim 13, Kempitiya teaches a method for controlling a drive circuit (Fig. 6, 606) that drives and controls a voltage-driven switching element (Fig. 6, 602), the method comprising:
injecting a charge into a gate of the voltage-driven switching element or extracting the charge from the gate by pulse driving of an on-circuit (Fig. 6, 620) or an off-circuit (Fig. 6, 624) of the voltage-driven switching element; and
controlling a switching time of the voltage-driven switching element (Fig. 6, 604).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6, 8, 11, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kempitiya in view of Mitchell US 4780656 A (Hereinafter “Mitchell”).
Regarding Claim 2, Kempitiya teaches the drive circuit according to claim 1,
Kempitiya does not expressly disclose wherein a pulse pattern driving the on-circuit or the off-circuit is held as a table.
However, Mitchell teaches a pulse pattern driving is held as a table (Mitchell Col. 2, lines 47-49, The microprocessor 34, the ROM look-up tables 36 and the PWM waveform generator are referred to collectively as the "control logic.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a pulse pattern driving is held as a table as taught by Mitchell in the system of Kempitiya, for the purpose efficiently and swiftly selecting the proper control for the transistor to drive the load.
Regarding Claim 3, Kempitiya in view of Mitchell teaches the drive circuit according to claim 2, wherein the pulse pattern is selected based on at least one of a temperature of the voltage-driven switching element, an amount of current flowing through the voltage-driven switching element, a DC voltage supplied to the voltage- driven switching element, and voltage of a terminal of the voltage-driven switching element (Kempitiya Figs. 14-15).
Regarding Claim 4, Kempitiya in view of Mitchell teaches the drive circuit according to claim 2, wherein the pulse pattern is updated in synchronization with a switching cycle of the voltage-driven switching element (Kempitiya Figs. 14-15).
Regarding Claim 6, Kempitiya in view of Mitchell teaches the drive circuit according to claim 2, further comprising another on-circuit (Kempitiya Fig. 9, 926) and another off-circuit (Kempitiya Fig. 9, 924) that are different from the on-circuit and the off-circuit,
wherein the another on-circuit and off-circuit are turned on and off only once in a switching cycle of the voltage-driven switching element (Kempitiya Col. 11 Lines 39-54).
Regarding Claim 8, Kempitiya in view of Mitchell teaches the drive circuit according to claim 2, wherein a pulse pattern driving the on-circuit and a pulse pattern driving the off-circuit both exist during switching operation of the voltage-driven switching element (Kempitiya Col. 5 Line 65- Col. 6 Line 24).
Regarding Claim 11, Kempitiya in view of Mitchell teaches the drive circuit according to claim 2, wherein a switching time of the voltage-driven switching element is changed by changing the pulse pattern (Kempitiya Col. 5 Line 65- Col. 6 Line 24).
Regarding Claim 14, Kempitiya teaches the method for controlling the drive circuit according to claim 13,
Kempitiya does not expressly disclose wherein a pulse pattern driving the on-circuit or the off-circuit is held as a table.
However, Mitchell teaches a pulse pattern driving is held as a table (Mitchell Col. 2, lines 47-49, The microprocessor 34, the ROM look-up tables 36 and the PWM waveform generator are referred to collectively as the "control logic.").
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a pulse pattern driving is held as a table as taught by Mitchell in the system of Kempitiya, for the purpose efficiently and swiftly selecting the proper control for the transistor to drive the load.
Regarding Claim 15, Kempitiya in view of Mitchell teaches the method for controlling the drive circuit according to claim 14, wherein the pulse pattern is selected based on at least one of a temperature of the voltage-driven switching element, an amount of current flowing through the voltage- driven switching element, a DC voltage supplied to the voltage-driven switching element, and a voltage of a terminal of the voltage-driven switching element (Kempitiya Figs. 14-15).
Allowable Subject Matter
Claims 5, 7, and 9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chen et al. US 20170194954 A1 teaches a connection point of the npn-type bipolar transistor 28 and the pnp-type bipolar transistor 29 is connected to the gate of the IGBT 22b through a gate resistor 30.
Xu et al. US 20200153362 A1 teaches a secondary winding 48 has sections magnetically coupled with each of primary windings 46 and 47, and two ends of secondary winding 48 are connected in a gate loop for lower transistor 43 between a gate driver 50 and gate resistor 51. A secondary winding 49 has sections magnetically coupled with each of primary windings 46 and 47, and two ends of secondary winding 49 are connected in a gate loop for upper transistor 42 between a gate driver 52 and gate resistor 53.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORTEZ M COOK whose telephone number is (571)270-7954. The examiner can normally be reached Monday-Thursday 7:30-5pm.
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/CORTEZ M COOK/ Primary Examiner, Art Unit 2846