DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7-11 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Di Ventra et al. (US 2017/0316309).
With respect to claim 1,
Figures 1, 5 and 6A of Di Ventra disclose a self-organizing logic circuit, comprising:
a plurality of self-organizing logic gates (40);
at least one control circuit (14 of Figure 1) configured to selectively connect the self-organizing logic gates to embed a problem in the self-organizing logic gates (Paragraph 75); and
an output circuit configured to read a solution to the problem from the self-organizing logic gates (Paragraph 31).
With respect to claim 4,
Di Ventra further teaches wherein each of the self-organizing logic gates comprising: a plurality of physical terminals (42, 44), and a plurality dynamic correction circuits (48), each of the dynamic correction circuits configured to drive a state of one of the physical terminals based on a state of one or more other ones of the physical terminals (see dynamic correction module of claim 22).
With respect to claim 7,
Di Ventra further teaches wherein the self-organizing logic gates comprise: a plurality of self-organizing OR gates, and a plurality of self-organizing NOT gates (see Figures 13A-13C).
With respect to claim 8,
Di Ventra further teaches wherein the problem is a satisfiability problem (Paragraph 30).
With respect to claim 9,
Di Ventra further teaches wherein the self-organizing logic circuit is embodied on a single integrated circuit (see Figures 1 and 5 and Paragraph 56).
With respect to claim 10,
Di Ventra further teaches wherein the self-organizing logic gates consist of metal oxide semiconductor circuit elements (Paragraph 291).
With respect to claim 11,
Figures 1, 5 and 6A of Di Ventra disclose a self-organizing logic gate, comprising:
a plurality of physical terminals (42, 44); and
a plurality dynamic correction circuits (48), each of the dynamic correction circuits configured to drive a state of one of the plurality of physical terminals based on states of the remaining one or more physical terminals of the plurality of physical terminals (see dynamic correction module of claim 22),
wherein the plurality of dynamic correction circuits are configured to implement a logical OR operation of the self-organizing logic gate such that at least one of the plurality of physical terminals has a logic 1 state (Paragraph 141).
With respect to claim 17,
Di Ventra further teaches wherein the self-organizing logic gates consist of metal oxide semiconductor circuit elements (Paragraph 291).
With respect to claim 18,
Figures 1, 5 and 6A of Di Ventra disclose a method of solving a satisfiability problem, comprising:
embedding the satisfiability problem in a plurality of self-organizing logic gates by selectively connecting the self-organizing logic gates (Paragraph 75); and
reading a solution to the satisfiability problem from the self-organizing logic gates once the self-organizing logic gates have reached an equilibrium (Paragraph 31).
With respect to claim 19,
Di Ventra further teaches wherein the plurality of self-organizing logic gates include a plurality of self-organizing OR gates and a plurality of self-organizing NOT gates (see Figures 13A-13C).
With respect to claim 20,
Di Ventra further teaches embedding an other problem in at least some of the plurality of self-organizing logic gates; and reading a solution to the other problem from the self-organizing logic gates (Paragraph 33).
Allowable Subject Matter
Claims 2-3, 5-6, 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jany Richardson whose telephone number is (571)270-5074. The examiner can normally be reached Monday - Friday, 7:00am to 3:00pm.
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/JANY RICHARDSON/Primary Examiner, Art Unit 2844