DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
3. Applicant's arguments filed 01/07/2026 have been fully considered but they are not persuasive.
With respect to Applicant argument that “In Valentine, the periodic analog signal Vt is a separate signal from the selection signal Select and separate from the supply voltage of the light-emitting diodes” and Valentine therefore does not teach or suggest at least the features of each selection signal or supply voltage,,.periodic per interval, the examiner respectfully disagrees. Valentine teaches this limitation in figure 4, paragraph 0041-0042, the saw tooth wave is interpreted as a selection signal, see office action. The claims do not explicitly recite the selection signal select or supply voltage as argued. In fact, supply voltage Vµled utilized voltages that have spaced phases. The selection signal, sawtooth waves Vt utilize spaced apart phases. The saw tooth wave Vt is utilized to select portions of Vframe that are utilized for Vµled via a result of comparison. Thus, Valentine teaches independent claims as argued.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claim(s) 1-5, 7-9 and 11-23 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by VALENTINE (Pub No: US 2019/0306945 A1).
With respect to claims 1 and 15, Valentine teaches: display screen (paragraph 25 and figure 2: ''µLED display panel'') comprising
display circuits (paragraphs 25-27 and figure 2: ''µLED cells 230''), each display circuit comprising a light-emitting diode (paragraphs 25-28 and figure 2: "the µLEDs are driven with a current density that is larger than a threshold value''), a controllable current source (paragraphs 39-40 and figures3A-3B: "The amplitude of the current supplied to the µLED 350 is controlled by p-type transistor Tl. The p-type transistor is controlled by a reference voltage Vref) powering the light-emitting diode and a driver circuit( paragraphs 29-32 and figures 3A-3B: ''µLED controller 305'') suitable for providing a pulse-width modulated signal (paragraphs 29-32 and figures 3A-3B: Vµled), for controlling the current source(paragraph 29 and figures 3A-3B: "The driving signal generated by the µLED controller 305 has a set voltage amplitude and a duty cycle that is based on the value of Vset 325");
first electrodes (paragraphs 41-42, figures 3A-3B and figure 4: VT) connected to the driver circuits;
a circuit for providing a selection signal (paragraphs 41-42, figures 3A-3B and figure 4: "a sawtooth pulse is provided to comparator 310 as the global control waveform signal (VT)") to each first electrode for the selection of the display circuits connected to the first electrode;
second electrodes paragraphs 41-42, figures 3A-3B and 4: "data signal Vset'') connected to the driver circuits;
a circuit for providing analog data signals to the second electrodes (paragraph 29 and figures 3A-3B:"The µLED controller 305 receives as an input a data signal (Vset) 325"), the driver circuit of each display circuit including a storage circuit configured to store the analog data signal received by the driver circuit( paragraph 29 and figures 3A-3B: "The µLED controller 305 stores Vset 325 when the select signal 220 is asserted") and a circuit for comparison of the analog data signal and an analog periodic interval signal( paragraph 31 and figures 3A-3B: "The comparator 310 compares the value of the VT signal and the output of the analog sample and hold module 315 and generates an output based on the comparison'') (see figure 4: the sawtooth signal is discontinuous)) suitable for providing the pulse-width modulated control signal;
third electrodes connected to the driver circuits (paragraph 40 and figure 3B: "The p-type transistor Tl is further coupled between a supply voltage and the drain of the n-type transistor T2"); and
a circuit for supplying a power supply voltage (paragraph 40 and figure 3B: "the µLED 350 may comprise one element of a µLED array with a common anode connected to a positive supply voltage") of the light-emitting diodes to the third electrodes,
wherein each selection signal or the power supply voltage comprises spaced phases each containing the analog periodic interval signal (figure 4: discontinuous sawtooth signal VT).
With respect to claim 2, Valentine teaches a display pixel according to claim 1, wherein each selection signal comprises successive pulses, each display circuit further comprising a detection circuit configured to detect each pulse of the selection signal that the display circuit receives and wherein the storage circuit of the display circuit is configured to store the analog data signal received by the driver circuit on detection of each pulse (Figure 3B, paragraph 0034 and 0036, the gate-drain capacitance of the transistor Q1has the function of detecting each pulse of the signal VT).
With respect to claims 3, 16 and 17, Valentine teaches a display pixel according to claim 2, wherein each selection signal comprises the phases interposed in time between two successive pulses (Figure 4, the signal VT, paragraph 0041-0042).
With respect to claim 4, Valentine teaches a display pixel according to claim 3, wherein the selection circuit is configured to differentiate, in the selection signal the pulses from the analog signal periodic per interval (Figure 3B, the gate-drain capacitance of the transistor Q1 paragraph 0033-0037).
With respect to claims 5 and 19, Valentine teaches a display pixel according to claim 4 wherein the maximum amplitude of the pulses of the selection signal is greater than the maximum amplitude of the analog signal periodic per interval (Figure 4).
With respect to claim 7 and 20, Valentine teaches a display pixel according to claim 4, wherein the periodic of the analog signal periodic per interval on each interval is different from the duration of each pulse (Figure 4).
With respect to claims 8 and 18, Valentine teaches a display pixel according to claim 4, wherein the waveform of the pulses of the selection signal is different from the waveform of the analog signal periodic per interval over a period of the analog signal periodic per interval (figure 4).
With respect to claim 9, Valentine teaches a display pixel according to claim 8, wherein the detection circuit comprises a high-pass filter or a low-pass filter (Figure 3B).
With respect to claims 11 and 21, Valentine teaches a display pixel according to claim 2, wherein the pulses and the phases of the analog signal periodic per interval are of signs opposite with respect to a reference value (figure 4)
With respect to claims 12 and 22, Valentine teaches a display pixel according to claim 1, wherein the signal periodic per interval is triangular (Figure 4).
With respect to claims 13 and 23, Valentine teaches a display pixel according to claim 1, wherein the signal periodic per interval contains only successive ascending ramps or only successive descending ramps (Figure 4, paragraph 0042).
With respect to claim 14, Valentine teaches a display pixel according to claim 1, wherein the signal periodic per interval contains only successive ascending ramps or only successive descending ramps. (Figure 4, paragraph 0043).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
6. Claim(s) 6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over VALENTINE (Pub No: US 2019/0306944 A1) in view of LEE (Pub No: US 2023/0395021A1).
Valentine teaches all the limitations of claim 5,but does not explicitly teach wherein the detection circuit comprises two successive inverters having different inversion thresholds. However, this limitation is well known in the art as evidenced by LEE who teaches in figure 1-13, two successive inverters 220-230 having different inversion thresholds, paragraph 0091-0105. Therefore, before the application was filed, it would have been obvious to one of ordinary shill in art to incorporate the inverters as taught by LEE into Valentine display circuit because it would reduce power consumption.
With respect to claim 10, VALENTINE as modified by LEE teaches a display pixel according to claim 2, LEE further teaches wherein each driver circuit comprises a circuit for delivering a binary signal containing pulses simultaneous with the pulses of the selection signal (Figures 1-13, paragraphs 0091-0092).
Conclusion
7. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICK NESTOR EDOUARD whose telephone number is (571)272-7603. The examiner can normally be reached M-F: 7:30-6:00.
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/PATRICK N EDOUARD/ Supervisory Patent Examiner, Art Unit 2622
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