DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 5 objected to because of the following informalities:
Claim 1, “at the output” in line 9 should be -- at an output --; “said output voltage” in line 21 and 22 should be -- said first output voltage --. Note, also the same problem in claim 5. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Botti et al. (US 2017/0160316 and Botti hereinafter) in view of Bonne et al. (EP 2760093 and Bonne hereinafter) (cited by Applicants).
Regarding claim 1, Botti discloses an electronic device [fig. 6] provided with transistors [13b and 23b, fig. 6], the electronic device comprising; a control circuit [50] configured to evaluate the drain source resistance [RDSONLP] in an on state of at least one first transistor [13b] out of said transistors, the on or off state of the first transistor being controlled by a first control signal [gate control 13b] applied to a gate [gate 13b], said control circuit including: a first circuit [51] configured to measure drain source voltage [VDSLP] in the on state of the first transistor [abstract], the first circuit comprising a first operational amplifier [51] configured to produce at the output a first output voltage proportional [output 51] to a difference in potentials between a drain electrode potential [drain 13b] of the first transistor placed in the on state and a source electrode potential [source 13b] of the first transistor placed in the on state, a first switch element [52P] arranged between a given electrode out of said source [source 13b] and drain electrodes of the first transistor [drain 13b] and a first input of the first amplifier [input (+/-) 51], the first switch element being configured to couple the given electrode to the first input of the first amplifier consecutively to a placement of the first transistor in the on state, a circuit branch [branch 14, fig. 1] in which a load current [Iout] that is an image of a current passing through the first transistor [current pass through 13b] in the on state is capable of circulating. Botti does not explicitly discloses an evaluation stage configured to, on the basis of said load current and said output voltage, produce a first evaluation signal representative of a ratio between said output voltage and said load current and GaN transistors.
However, Bonne discloses [fig. 1] an evaluation stage [10] configured to, on the basis of load current [IA] and output voltage [output 9], produce a first evaluation signal representative of a ratio between said output voltage [Rdson=Vds/Ids; para. 0020-0031]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Botti by incorporating the invention as taught Bonne in order to provide protection and safety in the event of a fault occurring on the drive output. Botti in view Bonne does not discloses GaN transistors. Although Botti et al. uses MOS transistors instead of GaN transistors for the first transistor, it is just different type of transistor and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Regarding claim 2, Botti in view of Bonne discloses [fig. 1] wherein the evaluation stage of the control circuit includes a digital calculation module integrated into a microcontroller [2, fig. 1 of Bonne] or into an integrated FPGA circuit having a network of programmable cells or includes an analog divider or an analog multiplier.
Regarding claim 3, Botti in view of Bonne discloses wherein the control circuit further includes a protection circuit, the protection circuit including a first comparator to compare said first evaluation signal to a given threshold [comprising means to determining the resistance R.sub.dson between the drain and the source of the transistor when the device is in an operative state, and means to compare this value against an expected value , R.sub.dsonexp to determine if there is a fault. Par. 0014], the protection circuit being configured to, when said first evaluation signal exceeds said given threshold, emit a deactivation signal so as to maintain said first transistor off [The monitored value of Rdson may be compared to an expected value Rdsonex. In operation, if there is an unreasonable discrepancy between the actual and the expected value, it may be assumed that a fault has developed. In the event, an alert may be generated; alternatively, the device may be switched off. Para. 0018].
Regarding claim 4, Botti in view of Bonne discloses further comprising a first gate pilot circuit [circuit controls gate on/off signal] producing said first control signal, the deactivation signal being emitted at the input of said first gate pilot circuit.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Botti et al. in view of Bonne et al. further in view of Bernacchia et al. (US 2009/0021271 and Bernacchia hereinafter) further in view of Shekhawat (US 8385092).
Regarding claim 5, Botti in view of Bonne discloses all the features with respect to claim 1 as indicated above. Botti in view of Bonne further discloses wherein among said transistors there is at least one second transistor [23, fig. 6] coupled to the first transistor, a gate of the second transistor being controlled by a second control signal [control signal to 23b, fig. 6], the second control signal being, in phase opposition to the first control signal [fig. 7], said circuit branch being arranged between the first transistor and the second transistor so that the load current is the image of the current passing through the second transistor when the second transistor is in the on state, said control circuit further including: circuit [51] configured to measure a drain source voltage in the on state of the second transistor, the circuit comprising an operational amplifier [51], mounted in differential mode, called amplifier [a differential preamplifier 51], to produce at the output an output voltage [output 21] proportional to a difference in potential between a drain electrode potential [drain 23b] of the second transistor placed in the on state and a source electrode potential [source] of the second transistor placed in the on state, and a second switch element [52M] arranged between the source or drain electrode of the second transistor and an input of the second amplifier [input (-/+) 51], the second switch element being configured to couple the source or drain electrode of the second transistor and the input of the amplifier consecutively to a placement of the second transistor in the on state, said evaluation stage [Bonne fig. 1] of the control circuit being further configured to, on the basis of said load current and said output voltage, produce evaluation signal representative of a ratio between the output voltage of the second transistor and said load current. Botti in view of Bonne does not explicitly disclose a second circuit comprising a second operational amplifier.
However, Bernacchia discloses [see fig. 2a] a second amplifier [11/12] to produce an output voltage [output 21] proportional to a difference in potential between a drain electrode potential and a source electrode potential. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Botti in view of Bonnie by incorporating the invention as taught Bernacchia in order to be able to precisely measure the on-resistance of a transistor during operation for performing a calibration or recalibration of a current measurement of the load current through the transistor. Botti in view of Bonnie and Bernacchia does not explicitly disclose except for dead times,
However, Shekhawat discloses dead time in switching is necessary [cl. 5, ln 47-59]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Botti in view of Bonnie and Bernacchia by incorporating dead time as taught in Shekhawat in order to prevent shoot through [cl. 5, ln 47-59].
Regarding claim 6, Botti in view of Bonne and Bernacchia further in view of Shekhawat discloses wherein the control circuit includes a protection circuit and wherein the gate of the second transistor is controlled by a second gate pilot circuit [circuit controls gate on/off signal], the protection circuit including a comparator to compare said second evaluation signal to another given threshold [comprising means to determining the resistance R.sub.dson between the drain and the source of the transistor when the device is in an operative state, and means to compare this value against an expected value , R.sub.dsonexp to determine if there is a fault. Par. 0014], the protection circuit being further configured to, when the second evaluation signal exceeds said other given threshold, emit a second deactivation signal at the input of a second gate pilot circuit so as to maintain said second transistor off [The monitored value of Rdson may be compared to an expected value Rdsonex. In operation, if there is an unreasonable discrepancy between the actual and the expected value, it may be assumed that a fault has developed. In the event, an alert may be generated; alternatively, the device may be switched off. Para. 0018].
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Botti et al. in view of Bonne et al. further in view of Shekhawat.
Regarding claim 7, Botti in view of Bonne discloses all the features with respect to claim 1 as indicated above. Botti in view of Bonne further discloses wherein the first switch element is controlled by a measurement triggering signal [SWPRP], the control circuit further comprising a stage for controlling the signal of the first control signal [gate signal 13b] and of the measurement triggering signal to, consecutively to a change in state of the first control signal [pn signal] turning the first transistor on, trigger, after change, a state modification of the measurement triggering signal so as to turn the first switch element on and to, consecutively to a new state modification of the measurement triggering signal [off signal] turning the first switch element off, trigger a new state change of the control signal turning the first transistor off. Botti in view of Bonne does not explicitly discloses after a first determined delay. However, Shekhawat discloses dead time/delay in switching is necessary [cl. 5, ln 47-59]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Botti in view of Bonnie and Bernacchia by incorporating dead time as taught in Shekhawat in order to prevent shoot through [cl. 5, ln 47-59].
6. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Botti et al. in view of Bonne et al. further in view of Li et al. (CN 106571744A and Li hereinafter).
Regarding claims 9-10, Botti in view of Bonne discloses all the features with respect to claim 1 as indicated above. Botti in view of Bonne does not explicitly disclose the first transistor belonging to an arm of the power inverter and the first transistor belonging to a switching cell of the converter.
However, Li discloses [see figs. 1-2] a full bridge first transistor inverter and converter. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Botti in view of Bonne as taught Li in order to utilize well-known a full bridge converter or inverter.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Botti et al. in view of Bonne et al. further in view of Waller et al. (US 2013/0272547 and Waller hereinafter).
Regarding claim 8, Botti in view of Bonne discloses all the features with respect to claim 1 as indicated above. Botti in view of Bonne does not explicitly disclose wherein the first differential amplifier is powered between a first positive power supply potential and a second negative power supply potential via an external battery.
However, Waller discloses [see fig. 8] power amplifier [P1] is powered between a first positive power supply [B1] potential and a second negative power supply [G1] potential via an external battery [battery]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Botti in view of Bonne as taught Waller in order to utilize well-known differential amplifier.
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2842