Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (lDS) submitted are in compliance with the provisions of 37 CFR 1.97 and have been considered by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8, 13, 15, 17. 19 and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SAITO et al. (US 20240088175 A1, hereinafter “SAITO”).
.
The applied reference has a common assignee and applicants with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, SAITO teaches an imaging device (as illustrated by Fig. 15: an imaging device 4) comprising:
a pixel array section (as illustrated by Fig. 15: pixel array unit 11) configured to output a pixel signal obtained through photoelectric conversion of incident light (as illustrated by Fig.15, [0076]-[0077]: pixel array unit 11, a plurality of pixels is arranged in a two-dimensional manner. Each pixel generates a pixel signal S12 obtained by photoelectrically converting incident light on the basis of a plurality of types of pixel control signals S11 from the pixel control circuit 12);
a memory array section (as illustrated by Fig. 15: memory array unit 21) configured to output a convolution signal indicating a result of a multiply-accumulate operation on an input signal based on the pixel signal (as illustrated by Fig. 15, [0131]: the memory array unit 21, a plurality of memory cells is arranged in a two-dimensional manner. The memory array unit 21 outputs a convolution signal S15 indicating a result of a product-sum operation by an analog method or a digital method using the plurality of memory cells to the CIM read circuit 23 in one direction.);
and a common circuit common to at least one of input and output sides of the pixel array section and the memory array section (as illustrated by Fig. 15: Logic circuit 15, switch 41, CIM input control circuit 22 and input/output unit 33 are common circuit to the pixel array unit 11 and the memory array unit 21).
Regarding claim 2, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses further comprising: a first selection circuit configured to select an electrical connection between the pixel array section and the common circuit, or an electrical connection between the memory array section and the common circuit (as illustrated by Fig. 2, [0099])..
Regarding claim 3, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses wherein the pixel array section is disposed on a first substrate, and the memory array section is disposed on a second substrate stacked on the first substrate (as illustrated by Fig. 2, [0189]-[0190]: The switch 41 is arranged between the pixel signal processing circuit 13 and the CIM input control circuit 22.).
Regarding claim 4, SAITO teaches the imaging device according to claim 3, in addition SAITO discloses wherein an output direction of the pixel signal is different from an output direction of the convolution signal (as illustrated by Figs. 2, [0099]: S12 and S15).
Regarding claim 5, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses wherein the pixel signal and the convolution signal are each an analog signal ([0010]: At least one of the pixel signal or the convolution signal may be an analog signal.), and the common circuit includes an AD converter configured to convert the analog signal into a digital signal ([0087[&[0141]: In a case where the convolution signal S15 is of an analog type, the input signal via the signal wiring 72 is multiplied by the memory value, and then the charge is added thereto on the read wiring 73, and the convolution signal S15 is read to the CIM read circuit 23. At that time, the input signals may be collectively input to the entire signal wiring 72, and in a case where the CIM read circuit 23 is a column ADC. pixel signal processing circuit 13 performs correlated double sampling (CDS) processing for removing pixel-specific fixed pattern noise and analog to digital (AD) conversion processing on the pixel signals S12 read from the pixel array unit 11.).
Regarding claim 6, SAITO teaches the imaging device according to claim 5, in addition SAITO discloses wherein the common circuit includes a horizontal operation circuit configured to control the AD converter ([0088]: a horizontal drive circuit 14).
Regarding claim 7, SAITO teaches the imaging device according to claim 6, in addition SAITO discloses wherein a plurality of the horizontal operation circuits are provided for the single AD converter ([0088]: The horizontal drive circuit 14 includes, for example, a shift register, and sequentially outputs horizontal scan pulses to the pixel signal processing circuit 13).
Regarding claim 8, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses wherein the pixel array section has a plurality of pixels two-dimensionally arranged (as illustrated by Fig.15, [0076]-[0077]: pixel array unit 11, a plurality of pixels is arranged in a two-dimensional manner), the memory array section has a plurality of memory cells two-dimensionally arranged (as illustrated by Fig. 15, [0131]: the memory array unit 21, a plurality of memory cells is arranged in a two-dimensional manner.), and the common circuit includes a vertical drive circuit configured to select a pixel row and a memory cell row ([0089]-[0091] the logic circuit 15 generates a vertical synchronization signal, a horizontal synchronization signal and the like on the basis of the input clock signal, and supplies the signals to the pixel control circuit 12, the pixel signal processing circuit 13, the horizontal drive circuit 14, the CIM input control circuit 22, The CIM input control circuit 22 includes, for example, a shift register, and inputs a memory cell control signal S14 associated with the image signal S13 to each memory cell of the memory array unit 21 via memory cell drive wiring (not illustrated in FIG. 1). By the memory cell control signal S14, the CIM input control circuit 22 sequentially or collectively selects and scans the memory cells of the memory array unit 21, and outputs the convolution signal S15 obtained by a product-sum operation using memory values of the respective memory cells to the CIM read circuit 23.).
Regarding claim 13, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses wherein the common circuit includes a reference voltage generation circuit configured to generate a reference voltage within the imaging device ([0137]: A ramp signal RAMP of a triangular wave is input to an inverted input terminal. Each comparator 131 outputs a comparison result between the pixel signal S12 and the ramp signal RAMP. Each counter 132 is connected to an output terminal of the comparator 131.).
Regarding claim 15, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses wherein the common circuit includes a clock generation circuit configured to generate a clock for setting operating frequencies of the pixel array section and the memory array section ([0089]: the logic circuit 15 generates a vertical synchronization signal, a horizontal synchronization signal and the like on the basis of the input clock signal, and supplies the signals to the pixel control circuit 12, the pixel signal processing circuit 13, the horizontal drive circuit 14, the CIM input control circuit 22, the CIM read circuit 23 and the like.).
Regarding claim 17, SAITO teaches the imaging device according to claim 1, in addition SAITO discloses wherein the common circuit includes a signal processing circuit configured to process signals obtained through digital conversion of the pixel signal and the convolution signal (as illustrated by Fig.15, [0097]: The input/output unit 33 outputs signals sequentially input from the signal processing circuit 31 to the external image processing device).
Regarding claim 19, claim 19 has been analyzed with regard to claim 1 and is rejected for the same the same rationale as applied above.
Regarding claim 20, method claim 20 and apparatus claim 1 are related as method and apparatus of using same, with each claimed element's function corresponding to the claimed method step. Accordingly claim 20 is similarly rejected under the same rationale as applied above with respect to apparatus claim 1.
Allowable Subject Matter
Claims 9-12, 14, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204. The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638
Prosecution Insights