DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, Species IA (Claim 1-6, 8 and 10) in the reply filed on 08/21/2026 is acknowledged. The traversal is on the ground(s) that no disclosure was identified for epitaxial III-N stack on SOI substrate having buried insulator formed on top of trap rich layer and that the Examiner did not explain why Species IA-IC are patentably distinct and that the embodiments overlap. This is not found persuasive because unity requires a special technical feature. The features common to groups I and II are the structure of Claim 1, which claim 12 recites in method form. Verma discloses an SOI substrate (101 having a silicon support substrate (102) a trap rich layer (130) a silicon oxide box layer (104) over the trap rich layer (130) and silicon top surface (106 doped see S/D regions) Verma also discloses a GaN buffer layer (142) and an AlGaN layer (142) epitaxially grown on trap rich layer (130) of the SOI substrate (Fig. 1-2).This is the very combination Applicant contends was not shown. Also, features are taught by Yue et al. (US 2019/0198623 A1) [001, 0014, 0024, 0038] and Seacrist et al. (US 2020/0020766 A1) [0043,0054] as set fourth in the rejection of Claim 1. The common features therefore make no contributions over the prior art.
Further, the features that distinguish the species are different technical features addressing different problems, Species B (Claim 7) SiN layer between two silicon oxide layer (0055] and Species IC (claims 9 and 11) a spacer layer between the active III-N layers [0062], 0071] the embodiments do no overlap, for example in the SiO, buried insulator and the Si/SiC trap-rich alternatives. Overlap in features that are not special technical features does not establish unity.
The requirement is still deemed proper and is therefore made FINAL.
Claims 7, 9, 11-15 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group and/or Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 08/21/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-6, 8 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 recites “an epitaxial III-N semiconductor layer stack”, “a first active III-N layer” and a second active III-N layer. The specification gives the “III-N” designation mutually inconsistent meanings. [0030 of PGPuB] states that “ In the context of the present disclosure” Group II- nitride refers to compounds of Group III elements (B, Al, Ga, In) and nitrogen which is the ordinary meaning. [0031 of PGPub] uses the same definitional phrasing but states that each active III-N layer comprises “one or more of N,P, As” together with one or more of B, Al, Ga, In, and Tl. Under [0031], a “III-Layer” need not contain nitrogen at al (e.g. GaAs or InP). [0065-0066 of PGPub] refer to the same element as “ second active III-V layer”. Further, [0073 of PGPub] defines “III” to include Sc, Y and Lanthanide and Actinide series. These are Group 3 transition metals, not members of Group III set identified in [0030-0031].
An applicant acting as lexicographer must set out the redefinition with reasonable clarity (MPEP 2111.01 (IV). Where the specification supplies competing definitions of the same claim term, the claim fails to inform one of ordinary skill in the art of their scope with reasonable certainty (MPEP 2173.03,2173.05(a).
A POSITA cannot determine whether an AlGaAs/GaAs heterostructure supporting 2DEG on an n-type trap rich SOI substrate falls within Claim1.
For the purposes of examination, the Examiner will interpret “III-N” under the broader [0031] statement.
Claims 1-6, 8 and 10 are rejected as being dependent on Claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yue et al. (US 2019/0198623 A1) in view of Seacrist et al. (US 2020/0020766 A1).
Regarding Claim 1, Yue (Fig. 1, 3) discloses a semiconductor structure, comprising:
a Silicon-On-Insulator substrate (102 “silicon on insulator”) comprising:
a base layer comprising silicon (lower 102, Silicon);
a top layer (180/181);
an epitaxial III-N semiconductor layer stack (104-112) on top of the Silicon-On-Insulator substrate (102) [0014, 0019-0025,0061-0066], the epitaxial III-N semiconductor layer stack comprising an epitaxial active layer; wherein
the epitaxial active layer comprises:
a first active III-N layer formed on top of (“108 GaN channel layer over buffer layer 106 and 104 on upper surface 103 consistent with indirect construction of “on top of”) the top layer;
a second active III-N layer (AlGaN 110) formed on top of the first active III-N layer (108); with
a two-dimensional Electron Gas (2-Deg channel 109) between the first active III-N layer and the second active III-N layer [0024] (Fig. 1
; and wherein:
the top layer comprises n-type doped silicon (n-type species (P, As, Sb, Bi) in doped region 180 at upper surface of 103 (Fig. 3A) Alternativly, an n-typer epitaxial Si layer 308/181 Fig. 5B, 5B); and
the intermediate layer comprises:
a trap-rich layer; and
a buried insulator formed on top of the trap-rich layer.
Yue does not explicitly disclose an intermediate layer formed on top of the base layer; a top layer formed on top of the intermediate layer, the intermediate layer comprises: a trap-rich layer; and a buried insulator formed on top of the trap-rich layer.
Seacrist (Fig. 2, 3) discloses a Silicon-On-Insulator substrate (20) comprising:
a base layer comprising silicon (22); an intermediate layer (trap-rich layer 28 and dielectric layer 24) (Fig. 2) formed on top of the base layer (22); and a top layer (26) formed on top of the intermediate layer (28, 24); the intermediate layer comprises: a trap-rich layer (28); and a buried insulator (24) formed on top of the trap-rich layer (28). [0014, 0026, 0027, 0042, 0051]. Seacrist further discloses epitaxial layer comprising GaN deposited on top layer 26. [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Yue in view of Seacrist such that an intermediate layer formed on top of the base layer; a top layer formed on top of the intermediate layer, the intermediate layer comprises: a trap-rich layer; and a buried insulator formed on top of the trap-rich layer in order to reduce parasitic losses and improve RF performance of its III-N device [0012, 0033], prevent formation of parasitic surface conduction layer that lowers effective substrate resistivity and increases RF losses, substrate non-linearity, and cross talk. [0024].
Regarding Claim 2, Yue in view of Seacrist discloses the semiconductor structure of claim 1, a
wherein an n-type doping concentration of the top layer is within the range of 1.10.sup.15 cm.sup.−3 to 5.10.sup.15 cm.sup.−3. (“the dopant concentration of n-type ion species in the doped region 180 may be between about 5×10.sup.15 cm.sup.−3 and about 1×10.sup.18 cm.sup.−3 “). [0016, 0038 Yue]
Yue in view of Seacrist does not explicitly disclose an n-type doping concentration of the top layer is within the range of 1.10.sup.15 cm.sup.−3 to 5.10.sup.15 cm.sup.−3.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Yue in view of Seacrist such that an n-type doping concentration of the top layer is within the range of 1.10.sup.15 cm.sup.−3 to 5.10.sup.15 cm.sup.−3 since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. MPEP 2144.05(I)
Regarding Claim 3, Yue in view of Seacrist discloses the semiconductor structure of claim 1, wherein
Yue in view of Seacrist does not explicitly disclose a thickness of the top layer is between 50 nm and 200 nm.
However, Seacrist discloses a thickness of the top layer (26) is between about 20 nanometers and about 1.5 micrometers [0053 and thin film device layers of about 0.01-0.20 micrometers [0004].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Yue in view of Seacrist such that a thickness of the top layer is between 50 nm and 200 nm since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. MPEP 2144.05(I)
Regarding Claim 5, Yue in view of Seacrist discloses the semiconductor structure of claim 1, wherein
the buried insulator comprises silicon dioxide [0042,0044, 0036 Seacrist] and wherein
the trap-rich layer comprises silicon. [0038, Claims 22-23; Seacrist]
Regarding Claim 6, Yue in view of Seacrist discloses the semiconductor structure claim 1, wherein
the buried insulator comprises silicon dioxide [0042, 0036 Seacrist] and wherein
Yue in view of Seacrist does not explicitly disclose that the trap-rich layer comprises amorphous silicon carbide.
However, Seacrist discloses the trap-rich layer comprises materials that may be polycrystalline or amorphous include silicon (Si), silicon germanium (SiGe), silicon doped with carbon (SiC) and that SiC Is a compound of silicon and carbon, which may vary in molar ratio of silicon and carbon [0038, Claim 23].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Yue in view of Seacrist such that the trap-rich layer comprises amorphous silicon carbide since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Regarding Claim 8, Yue in view of Seacrist discloses the semiconductor structure of claim 1,
Yue in view of Seacrist does not explicitly disclose a thickness of the buried insulator is comprised between 100 nm and 500 nm.
However, Seacrist discloses a thickness of the buried insulator (24) is comprised between about 0.1 micrometers and about 1 micrometer. [0042] and that the insulating layer may be about 50-400nm or about 100-400nm thick, for example about 100nm or about 200nm [0044].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Yue in view of Seacrist such that t a thickness of the buried insulator is comprised between 100 nm and 500 nm since it has been held that the general conditions of a claim are disclosed in a prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. MPEP 2144.05(I)
Regarding Claim 10, Yue in view of Seacrist discloses the semiconductor structure of claim 1, wherein
the first active III-N layer comprises gallium nitride (108 is GaN [0023, 0064 Yue] and wherein the second active III-N layer comprises aluminum gallium nitride. (110, AlGaN [0024 Yue].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yue et al. (US 2019/0198623 A1) in view of Seacrist et al. (US 2020/0020766 A1) and further in view of Radosavljevic et al (US 2020/0411678 A1)
Regarding Claim 4, Yue in view of Seacrist discloses the semiconductor structure of claim 1, wherein
Yue in view of Seacrist does not explicitly disclose an orientation of the n-type doped silicon of the top layer is (111).
Radosavljevic (Fig. 2) discloses an SOI substrate whose first (top) substrate layer 215, on which III-N material is grown has (111) crystal orientation. [0026].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a semiconductor structure in Yue in view of Seacrist and Radosavljevic such that an orientation of the n-type doped silicon of the top layer is (111) in order to better match III-N material with wurtzite crystallinity and is therefore advantageous for seeding heteroepitaxial growth [0026-0030, 0034]
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Briere et al. US 2010/0096668 A1) discloses SOI substrate having top layer with (111) orientation.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
