DETAILED ACTION
This Office action is in response to the application filed on 14 June 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2, 9, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Olivier Trescases et. al (IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 58, Issue: 1, January 2011; hereafter “Olivier”) in view of Michael Krug et. al (US 20220334155A1; hereafter “Krug”).
-Regarding claim 1:
Olivier discloses:
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switching control signal (above Fig. 2; red arrow) used to control charging of an inductor (above Fig. 2; VL) of the switching power supply; determining a number of bits produced in the bitstream that are one bits during a specified time duration (Introduction; a one-bit sigma delta DAC was used to meet the tight resolution requirements of mixed-signal CPM; and ADC conversion time in table I);
Krug discloses:
A method of operating a switching power supply (Krug’s Fig. 2; 200), the method comprising: monitoring an input voltage and an output voltage of the switching power supply (paragraphs 0003,0004,0005; this disclosure is directed to techniques for monitoring a voltage…); producing a bitstream (Krug’s Fig. 1; 125 and paragraph 0036; via external bitstream) using the input voltage, the output voltage, and and changing operation (Krug’s Fig. 2; Host controller 230) of the switching power supply according to the determined number of bits (paragraph 0004; The processing circuitry is further configured to determine a measurement time to measure the voltage at the voltage rail based on the switching signal and generate, using an ADC,).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Olivier such that a commonly used voltage monitoring techniques with an analog to digital converter (ADC) described in Krug is applied to the switching power supply device for monitoring the efficiency of power supply operation. Doing so allows for improving the efficiency of operating the switching power supply by monitoring the efficiency of the switching power supply in a given system operating condition.
-Regarding claim 2;
Krug discloses:
The method of claim 1, wherein the producing the bitstream includes producing the bitstream (Krug’s Fig. 2; 227, Data) by applying the input voltage (Krug’s Fig. 1; 108), the output voltage (Krug’s Fig. 2; AIP, AIN), and the switching control signal (Krug’s Fig. 2; arrow from Proc. Circuitry to ADC) to a sigma-delta analog-to-digital converter (ADC) circuit (Krug’s Fig. 2; ADC).
-Regarding claim 9;
Olivier discloses:
used to control charging of an inductor(above Fig. 2; VL) of the switching converter circuit; and a sigma-delta analog-to-digital converter (ADC) circuit(above Fig. 2; ADC) to output a serial bitstream
Krug discloses:
A circuit to monitor efficiency (Krug’s Fig. 2; ADC and Proc. Circuitry) of a switching converter circuit, the circuit comprising :a first input to receive an output voltage (Krug’s Fig. 2; AIP, AIN) of the switching converter circuit; a second input to receive an input voltage (Krug’s Fig. 1; 108) of the switching converter circuit; a third input to receive a switching control signal (Krug’s Fig. 2; arrow from Proc. Circuitry to ADC) to output a serial bitstream representative (Krug’s Fig. 2; 227, Data) of efficiency of the switching converter circuit using the input voltage, the output voltage, and the switching control signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Olivier such that a commonly used voltage monitoring techniques with an analog to digital converter (ADC) described in Krug is applied to the switching power supply device for monitoring the efficiency of power supply operation. Doing so allows for improving the efficiency of operating the switching power supply by monitoring the efficiency of the switching power supply in a given system operating condition.
-Regarding claim 12:
Krug discloses:
The circuit of claim 9, including logic circuitry connected to the output of the sigma-delta ADC (paragraph 0018; As such, systems configured to recalculate the set of measured voltage values from the ADC may rely on external additional components (e.g., a filter, a data store, and/or logic circuitry)) and configured to determine a number of bits of the serial bitstream that are one bits in the bitstream during a specified time duration.
-Regarding claim 14:
Olivier discloses:
An electronic system, the system comprising :a switching converter circuit (above Fig.2 ) including: an input to receive an input voltage (above Fig.2 ; Vin) and an output to provide an output voltage(above Fig.2 ; Vout); at least one inductor (above Fig.2 ; VL); and a switch control circuit to produce a switching control signal used to control charging of an inductor (above Fig.2 ; red arrow) of the switching converter circuit to produce the output voltage; a sigma-delta analog-to-digital converter (ADC) circuit (above Fig. 2; ADC)
Krug discloses:
a first input connected to the output of the switching converter circuit (Krug’s Fig. 2; AIP, AIN); a second input connected to the input of the switching converter circuit(Krug’s Fig. 1; 108); a third input connected to a switch control circuit of the switching converter circuit (Krug’s Fig. 2; arrow from Proc. Circuitry to ADC); and a bitstream representative of efficiency of the switching converter circuit(Krug’s Fig. 2; 227, Data) using the input voltage the output voltage, and the switching control signal of the switching converter circuit; and a controller circuit configured to change operation (Krug’s Fig. 2; Host controller 230) of the switching converter circuit according to the generated bitstream(Krug’s Fig. 2; 227, Data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Olivier such that a commonly used voltage monitoring techniques with an analog to digital converter (ADC) described in Krug is applied to the switching power supply device for monitoring the efficiency of power supply operation. Doing so allows for improving the efficiency of operating the switching power supply by monitoring the efficiency of the switching power supply in a given system operating condition.
Allowable Subject Matter
Claims 3-8, 10,11,13, 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
The following is a statement of reasons for the indication of allowable subject matter:
-with respect to claim 3:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about a controlling source current for the sigma-delta ADC circuit.
-with respect to claim 4:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about a ratio that includes the determined number of bits that are one bit and a total number of bits in the bitstream.
-with respect to claim 5:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about multiple segments of at least one segmented power transistor.
-with respect to claim 6:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about a dead time between activation of the first power transistor and the second power transistor according to the according to the determined number of bits.
-with respect to claim 7:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about a voltage applied to a control input of at least one of the first and second power transistors according to the according to the determined number of bits.
-with respect to claim 8:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about a specified threshold output current value; detecting a change in the number of bits between a first specified time duration and a second specified time duration.
-with respect to claim 10:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about a first and a second switches connection into the sigma-delta ADC circuit.
-with respect to claim 11:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about an integrator stage; a one-bit analog-to-digital converter (ADC) stage connected to the integrator stage; and a feedback circuit path.
-with respect to claim 13:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about the logic circuitry is configured to determine a ratio including the determined number of bits that are one bit in the bitstream during a specified time duration and a total number of bits in the bitstream during the specified time duration.
-with respect to claim 15:
the prior arts in Krug, and Olivier disclose the claimed invention in basic claims but do not further disclose about the controller circuit includes logic circuitry.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEUNG HO CHOI whose telephone number is (571)272-8188. The examiner can normally be reached Monday-Thursday, 7:30 AM - 5:30 PM ET.
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/SEUNG HO CHOI/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838