DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 30 rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because Claim 30 recites a “computer readable medium” but does not specify that it is non-transitory. The specification of the present application recites: “Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to (1) tangible computer- readable storage media, which is non-transitory or (2) a communication medium such as a signal or carrier wave.” [0106] (emphasis added). During patent examination, the pending claims must be “given their broadest reasonable interpretation consistent with the specification.” (MPEP 2111). Therefore, a computer readable medium may be a transitory signal. A “transitory, propagating signal does not fall within any statutory category.” (MPEP 2106.03). Therefore, Claim 30 is directed to non-statutory subject matter. The Examiner suggests amending Claim 30 to read “A non-transitory computer-readable medium storing computer executable code …” to overcome the §101 rejection.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The limitations in question are: “means for obtaining pixel information”, “means for calculating a depth value”, “means for identifying”, “means for configuring a pattern mask”, “means for outputting” in Claim 29.
The limitations recite the word “means”.
The limitations all contain functional language (e.g. obtaining, calculating, identifying).
There is no corresponding structure/material/acts recited to perform the function. The Examiner notes that what would be corresponding structure (memory and/or a processor) is missing in Claim 29, though it is present in Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 4, 10, 13, 14, 16, 17, 19, 20, 21, 22, 29, and 30 are rejected under 35 U.S.C 102(a)(1) as being unpatentable over Dimitrov (US 20190206023 A1).
Regarding claim 1:
Dimitrov teaches:
An apparatus for graphics processing, comprising:
a memory; and
at least one processor coupled to the memory and, based at least in part on first information stored in the memory (Dimitrov: A method for rendering graphics frames allocates rendering work to multiple graphics processing units (GPUs) that are configured to allow access to pages of data stored in locally attached memory of a peer GPU, Abstract), the at least one processor is configured to:
obtain pixel information for a plurality of pixels in at least one frame (Dimitriv: a given frame to be rendered is partitioned into regions (e.g., rectangular regions) [0022]; and alternatively; Dimitrov: In other embodiments, the frame is partitioned into regions that may overlap by one or more pixels [0022]), the at least one frame being included in a plurality of frames in a scene (Dimitrov: In various embodiments, method 100 is implemented in the context of a graphics system, configured to render graphics frames [0025]);
calculate a depth value for each of a first set of pixels of the plurality of pixels (Dimitrov: The ZROP unit 354 receives a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 325 [0091]);
identify whether each of the first set of pixels (Dimitrov: rectangular regions 132(1), 132(3), 132(5), and 132(7) [0045]) or a second set of pixels, or both, is occluded by at least one occluding object in the scene (Dimitrov: In one embodiment, z-testing may also be performed to determine if the geometric primitive is occluded by other geometric primitives that have already been rasterized. [0120]), wherein the second set of pixels (Dimitrov: rectangular regions 132(0), 132(2), 132(4), 132(6), and 132(8) [0045]) is included in the plurality of pixels (Dimitrov: rectangular regions 132 [0051]);
configure a pattern mask configuration associated with a visibility mask (see Note 1B) for the plurality of pixels (Dimitrov: In one embodiment, the rectangular regions 132 are each allocated to one of two different GPUs, according to a checkerboard pattern covering the screen space scene 130 [0045]), the pattern mask configuration including a first pattern portion corresponding to the first set of pixels (Dimitrov: rectangular regions 132(1), 132(3), 132(5), and 132(7) may be assigned to a GPU 139(0) (e.g., the first GPU) [0045]; see Note 1A) and a second pattern portion corresponding to the second set of pixels (Dimitrov: rectangular regions 132(0), 132(2), 132(4), 132(6), and 132(8) may be assigned to a GPU 139(1) (e.g., the second GPU) [0045]); and
output, based on the pattern mask configuration (see Note 1C), an indication of the depth value for each of the first set of pixels (see Note 1A) and coverage information for each of the first set of pixels or the second set of pixels, or both (Dimitrov: The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine may be transmitted [0084]), wherein the coverage information is associated with whether each of the first set of pixels or the second set of pixels, or both, is occluded by the at least one occluding object in the scene (Dimitrov: The rasterization stage 660 may also compute a coverage mask for a plurality of pixels that indicates whether one or more sample locations for the pixel intercept the geometric primitive. [0120])
Note 1A: Dimitrov teaches that an updated depth buffer is generated based on a depth test associated with a pixel fragment in [0091]: “The ZROP unit 354 receives a depth for a sample location associated with a pixel fragment from the culling engine of the raster engine 325. The ZROP unit 354 tests the depth against a corresponding depth in a depth buffer for a sample location associated with the fragment. If the fragment passes the depth test for the sample location, then the ZROP unit 354 updates the depth buffer and transmits a result of the depth test to the raster engine 325.” One of ordinary skill in the art would understand that a depth buffer stores depth data for each pixel, and therefore, updating and outputting said depth buffer is analogous to outputting an indication of the depth value for each of the first set of pixels.
Note 1B: Dimitrov determines “potentially visible primitives” at the SCC stage 650: “All potentially visible geometric primitives are then transmitted to the rasterization stage 660.” [0119]. Said primitives are included in a “screen space scene 130” that is divided in two by a checkerboard mask: “The screen space scene 130 may include primitives (e.g., geometric primitives) such as triangles 134” [0045]; “the rectangular regions 132 are each allocated to one of two different GPUs, according to a checkerboard pattern covering the screen space scene 130.” [0045]. That is, Dimitrov teaches that a pattern mask configuration (checkerboard pattern) associated with a visibility mask (potentially visible primitives) is configured.
Note 1C: In Note 17A shown below, it is discussed that the ZROP is a component of each GPU. Dimitrov also teaches that “rendering work may be allocated between two or more GPUs using any technically feasible technique without departing the scope and spirit of various embodiments” and that “In one embodiment, the rectangular regions 132 are each allocated to one of two different GPUs, according to a checkerboard pattern covering the screen space scene 130.” In other words, because the depth testing is a function of each GPU, and the work may between each GPU split based on the checkerboard pattern, the output is based on the pattern mask configuration.
Regarding claim 2:
Dimitrov teaches:
The apparatus of claim 1 (as shown above), wherein the pattern mask configuration is a checkerboard mask configuration, wherein the first pattern portion is a first checkerboard portion and the second pattern portion is a second checkerboard portion, and wherein each of the first set of pixels includes a first pair of pixel coordinates in a set of pixel coordinates and each of the second set of pixels includes a second pair of pixel coordinates in the set of pixel coordinates (Dimitrov: the rectangular regions 132 are each allocated to one of two different GPUs, according to a checkerboard pattern covering the screen space scene 130. For example, rectangular regions 132(1), 132(3), 132(5), and 132(7) may be assigned to a GPU 139(0) (e.g., the first GPU) and rectangular regions 132(0), 132(2), 132(4), 132(6), and 132(8) may be assigned to a GPU 139(1) (e.g., the second GPU). [0045]; Dimitrov: see Fig. 1D).
Regarding claim 3:
Dimitrov teaches:
The apparatus of claim 2 (as shown above), wherein the first checkerboard portion corresponds to one or more first pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to one or more second pixels of the checkerboard mask configuration or wherein the first checkerboard portion corresponds to the one or more second pixels of the checkerboard mask configuration and the second checkerboard portion corresponds to the one or more first pixels of the checkerboard mask configuration, and wherein the one or more first pixels are interleaved with the one or more second pixels, such that the one or more first pixels and the one or more second pixels are distributed in an interleaving pattern (Dimitrov: a given frame to be rendered is partitioned into regions (e.g., rectangular regions) forming a checkerboard pattern, with non-overlapping adjacent regions sharing a common edge in the checkerboard pattern generally assigned to different GPUs [0022]; Dimitrov: see Fig. 1D; see Note 3A).
Note 3A: Dimitrov showcases in Fig. 1D how the regions 132 are separated. Each GPU has regions distributed in an interleaving pattern.
Regarding claim 4:
Dimitrov teaches:
The apparatus of claim 2 (as shown above), wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to an odd value, and wherein a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to an even value (see Note 4A).
Note 4A: Pictured below is an edited variant of Figure 1D of Dimitrov to include coordinates. The pixel coordinates of GPU 139(0) are odd, while the pixel coordinates of GPU 139(1) are even.
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Fig. 1D of Dimitrov edited to show coordinate values and their sums.
Regarding claim 10:
Dimitrov teaches:
The apparatus of claim 1, wherein the at least one processor is further configured to:
retrieve the depth value for the first set of pixels (Dimitrov: The ZROP unit 354 receives a depth for a sample location associated with a pixel fragment [0091]) and the coverage information for the first set of pixels and the second set of pixels (Dimitrov: The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine may be transmitted to the culling engine [0084]; see also Note 18A).
Regarding claim 13:
Dimitrov teaches:
The apparatus of claim 1 (as shown above), wherein the at least one processor is further configured to:
configure the visibility mask prior to the configuration of the pattern mask configuration associated with the visibility mask (Dimitrov: All potentially visible geometric primitives are then transmitted to the rasterization stage 660. [0119]; see Note 13A).
Note 13A: Dimitrov teaches rasterization stage 660 is when the coverage mask will be generated: “The rasterization stage 660 may also compute a coverage mask” [0120]. In [0119] cited above, Dimitrov determines potentially visible primitives before this stage. The potentially visible set of primitives is understood to be analogous to a visibility mask.
Regarding claim 14:
Dimitrov teaches:
The apparatus of claim 1 (as shown above), wherein an amount of the first set of pixels is substantially equal to half of the plurality of pixels and an amount of the second set of pixels is substantially equal to half of the plurality of pixels, such that the amount of the first set of pixels is substantially equal to the amount of the second set of pixels (Dimitrov: Fig. 1D; see Note 14A).
Note 14A: Dimitrov teaches an example where the first set of pixels 131(0) masks 4 regions (or pixels, see Note 1A). The second set of pixels masks 5 regions. There were a total of 9 regions to start with in screen space scene 130.
Regarding claim 16:
Dimitrov teaches:
The apparatus of claim 1 (as shown above), wherein to output the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, the at least one processor is configured to:
store, in a system memory, the depth value for each of the first set of pixels (Dimitrov: the ZROP unit 354 updates the depth buffer and transmits a result of the depth test to the raster engine 325. [0091]; see Note 16A) and the coverage information for each of the first set of pixels or the second set of pixels, or both (Dimitrov: The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine may be transmitted to the culling engine [0084]; see Note 16A).
Note 16A: Transmission of data requires at least short-term storage in system memory.
Regarding claim 17:
Dimitrov teaches:
The apparatus of claim 1 (as shown above), wherein to output the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, the at least one processor is configured to:
transmit, to at least one component of a graphics processing unit (GPU) or a central processing unit (CPU), the indication of the depth value for each of the first set of pixels (Dimitrov: the ZROP unit 354 updates the depth buffer and transmits a result of the depth test to the raster engine 325. [0091]; see Note 17A) and the coverage information for each of the first set of pixels or the second set of pixels, or both (Dimitrov: The plane equations are transmitted to the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine may be transmitted to the culling engine [0084]).
Note 17A: The ZROP is part of the ROP 350 shown in Fig. 3B of Dimitrov. The ROP is part of Partition Unit 280 shown in Fig. 2 of Dimitrov. The Partition unit is part of PPU 200. Dimitrov teaches that the PPU is analogous to a GPU: “In one embodiment, the PPU 200 is a graphics processing unit (GPU)” [0070].
Regarding claim 19:
Claim 19 is substantially similar to Claim 1, and is therefore rejected for similar reasons, with the following notable differences:
Claim 19 is a method claim instead of an apparatus claim. In showing above that Dimitrov teaches the apparatus in Claim 1, Dimitrov necessarily teaches the corresponding method.
Regarding claim 20:
Claim 20 is substantially similar to Claim 2, and is therefore rejected for similar reasons, with the following notable differences:
Claim 20 is a method claim instead of an apparatus claim. In showing above that Dimitrov teaches the apparatus in Claim 2, Dimitrov necessarily teaches the corresponding method.
Regarding claim 21:
Claim 21 is substantially similar to Claim 3, and is therefore rejected for similar reasons, with the following notable differences:
Claim 21 is a method claim instead of an apparatus claim. In showing above that Dimitrov teaches the apparatus in Claim 3, Dimitrov necessarily teaches the corresponding method.
Regarding claim 22:
Dimitrov teaches:
The method of claim 20 (as shown above), wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to a first odd value and a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to a first even value (see Note 4A above); or
wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to a second even value and a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to a second odd value.
Regarding claim 29:
Claim 29 is substantially similar to Claim 1, and is therefore rejected for similar reasons, with the following notable differences:
Claim 29 teaches an apparatus that instead includes a “means” for performing the method steps instead of a memory and processor. In showing above that Dimitrov teaches the apparatus in Claim 1, Dimitrov necessarily teaches the corresponding apparatus as well.
Regarding claim 30:
Claim 30 is substantially similar to Claim 1, and is therefore rejected for similar reasons, with the following notable differences:
Claim 30 is a computer-readable medium (CRM) claim instead of an apparatus claim. Dimitrov teaches a CRM: “The computer readable medium includes instructions that, when executed by a processing unit, perform the method,” [0004].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C 103 as being unpatentable over Dimitrov (US 20190206023 A1).
Regarding claim 5:
Dimitrov teaches:
The apparatus of claim 2 (as shown above), wherein a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to an even value, and wherein a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to an odd value.
Note 5A: In the mapping of claim 4, it was shown that a set of pixels may be assigned such that a sum of the first pair of pixel coordinates for each of the first set of pixels is equal to an odd value, and wherein a sum of the second pair of pixel coordinates for each of the second set of pixels is equal to an even value. It would be obvious to one of ordinary skill in the art to assign the regions such that the mapping is swapped, i.e., GPU 139(0) receives the map of GPU 139(1) and vice-versa. Specifically, the Examiner understands this to be Reversal of Parts (MPEP 2144.04 VI(a)) or alternatively, Rearrangement of Parts (MPEP 2144.04 VI(c)) because the matter not explicitly disclosed in Dimitrov is merely that the sets of pixels are swapped relative to how they are displayed in Fig. 1D.
Claims 6, 7, 8, 9, 23, 24, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Dimitrov (US 20190206023 A1) in view of Davies (US 20190295313 A1; from Applicant’s IDS).
Regarding claim 6:
Dimitrov teaches:
The apparatus of claim 1 (as shown above),
Dimitrov fails to explicitly teach:
wherein the coverage information for each of the first set of pixels and each of the second set of pixels corresponds to a binary coverage mask.
Davies teaches:
wherein the coverage information for each of the first set of pixels and each of the second set of pixels corresponds to a binary coverage mask (Davies: The coverage mask has one bit per sample in the tile, and each bit is set to one if it is covered by the triangle and does not unambiguously fail the conservative depth test in the depth culling unit. [0137]).
Regarding claim 7:
Dimitrov in view of Davies teaches:
The apparatus of claim 6 (as shown above), wherein the at least one processor is further configured to:
generate the binary coverage mask prior to the output of the indication of the coverage information for each of the first set of pixels and each of the second set of pixels (Dimitrov: The rasterization stage 660 may also compute a coverage mask for a plurality of pixels [0120]; see Note 7A), and
Davies teaches:
wherein to output the indication of the coverage information for each of the first set of pixels and each of the second set of pixels, the at least one processor is configured to: store the binary coverage mask (Davies: A buffer 1734 may store the coverage mask as well. [0169]).
Note 7A: Fig. 9 of the present application showcases that the indication of the depth and coverage information is utilized to perform occlusion culling. Dimitrov teaches that: “… the coarse raster engine [generates] coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine may be transmitted to the culling engine where fragments associated with the primitive that fail a z-test are culled”. The output of the coarse raster engine is analogous to an indication of the coverage information, and is similarly used for culling based on z-testing.
Regarding claim 8:
Dimitrov in view of Davies teaches:
The apparatus of claim 6 (as shown above), wherein the coverage information for each of the first set of pixels and each of the second set of pixels that is occluded by the at least one occluding object corresponds to a first value in the binary coverage mask, and the coverage information for each of the first set of pixels and each of the second set of pixels that is not occluded by the at least one occluding object corresponds to a second value in the binary coverage mask (Davies: The coverage mask has one bit per sample in the tile, and each bit is set to one if it is covered by the triangle [0137]; see Note 8A).
Note 8A: Davies teaches in Fig. 15A that a coverage mask may have either a 0 or 1 for each tile.
Regarding claim 9:
Dimitrov in view of Davies teaches:
The apparatus of claim 8 (as shown above), wherein the first value in the binary coverage mask corresponds to a bit value of 1, and the second value in the binary coverage mask corresponds to a bit value of 0 (Davies: Fig. 15A-D; see Note 8A).
Regarding claim 23:
Claim 23 is substantially similar to Claim 6, and is therefore rejected for similar reasons, with the following notable differences:
Claim 23 is a method claim instead of an apparatus claim. In showing above that Dimitrov in view of Davies teaches the apparatus in Claim 6, Dimitrov in view of Davies necessarily teach the corresponding method.
Regarding claim 24:
Claim 24 is substantially similar to Claim 7, and is therefore rejected for similar reasons, with the following notable differences:
Claim 24 is a method claim instead of an apparatus claim. In showing above that Dimitrov in view of Davies teaches the apparatus in Claim 7, Dimitrov in view of Davies necessarily teach the corresponding method.
Regarding claim 25:
Claim 25 is substantially similar to a concatenation of Claims 8 and 9, and is therefore rejected for similar reasons, with the following notable differences:
Claim 25 is a method claim instead of an apparatus claim. In showing above that Dimitrov in view of Jouppi teaches the apparatus in Claim 9 (which is dependent on claim 8), Dimitrov in view of Jouppi necessarily teach the corresponding method.
Claims 11, 12, 26 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Dimitrov (US 20190206023 A1) in view of Jouppi (US 6204859 B1; see attached document for paragraph numbers).
Regarding claim 11:
Dimitrov teaches:
The apparatus of claim 10 (as shown above), wherein the at least one processor is further configured to:
perform an occlusion culling calculation based on the depth value for the first set of pixels and the coverage information for the first set of pixels and the second set of pixels (Dimitrov: In one embodiment, z-testing may also be performed to determine if the geometric primitive is occluded by other geometric primitives that have already been rasterized. [0120]; see Note 11A),
wherein the occlusion culling calculation is associated with whether any of the first set of pixels or any of the second set of pixels are not occluded by the at least one occluding object in the scene (see Note 11A),
Note 11A: One of ordinary skill in the art would understand “z-testing” as taught by Dimitrov in [0120] to be analogous to “perform[ing] an occlusion culling calculation based on the depth value”. Additionally, Dimitrov teaches that the calculation is performed to “determine if the geometric primitive is occluded by other geometric primitives that have already been rasterized,” indicating that the calculation will be associated with whether “any of the first set of pixels or any of the second set of pixels are not occluded by the at least one occluding object”.
Dimitrov fails to explicitly teach:
wherein each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than an occluding depth map value,
wherein each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value.
Jouppi teaches:
wherein each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than an occluding depth map value (Jouppi: If the new fragment has a smaller Z-depth value than the Z-depth value of a stored fragment for any covered subpixel sample S1-S4, then the new fragment is in front of that stored fragment and, consequently, is visible, Paragraph 113),
wherein each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value (Jouppi: Conversely, the "0" value in bit 626 of the coverage mask 620 indicates that the fragment 302 is not visible at the subpixel sample S1, Paragraph (104); see Note 11B).
Note 11B: Jouppi teaches: “Clearly, the role of each bit value can be reversed so that the "1" bit value indicates that the fragment is not visible at a given sample point, and that the "0" bit value indicates that the fragment is visible.”
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Jouppi with Dimitrov. Determining each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than an occluding depth map value, and that each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value, as in Jouppi, would benefit the Dimitrov teachings by using less storage while enabling hierarchical depth testing: “the invention avoids storing redundant data for the pixel 300 because only one instance of the fragment triple 310 is stored for the three subpixel samples S2-S4. By so doing, the storage requirements for fragment triples are considerably reduced,” (Jouppi, Paragraph (36)).
Regarding claim 12:
Dimitrov teaches:
The apparatus of claim 1 (as shown above),
Dimitrov fails to explicitly teach:
wherein each of the first set of pixels or each of the second set of pixels, or both, is occluded by the at least one occluding object or an occluder depth map if the pixel is covered by the at least one occluding object in the occluder depth map.
Jouppi teaches:
wherein each of the first set of pixels or each of the second set of pixels, or both, is occluded by the at least one occluding object or an occluder depth map if the pixel is covered by the at least one occluding object in the occluder depth map (Jouppi: The "1" value in bits 628, 630 and 632 of the coverage mask 620 link the subpixel samples S2-S4 to the stored fragment triple 310, indicating that the fragment 302 is visible at those sample points S2-S4, Paragraph (104); see Note 12A).
Note 12A: As best understood by the Examiner, the fragment being visible indicates that it occludes the subpixel sample (i.e., is drawn over the subpixel).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Jouppi with Dimitrov. Determining each of the first set of pixels is not occluded by the at least one occluding object if the depth value of the pixel is closer to a viewpoint of the scene than an occluding depth map value, and that each of the second set of pixels is not occluded by the at least one occluding object if the coverage information of the pixel is a non-zero value, as in Jouppi, would benefit the Dimitrov teachings by using less storage while enabling hierarchical depth testing: “the invention avoids storing redundant data for the pixel 300 because only one instance of the fragment triple 310 is stored for the three subpixel samples S2-S4. By so doing, the storage requirements for fragment triples are considerably reduced,” (Jouppi, Paragraph (36)).
Regarding claim 26:
Claim 26 is substantially similar to a concatenation of Claims 10 and 11, and is therefore rejected for similar reasons, with the following notable differences:
Claim 26 is a method claim instead of an apparatus claim. In showing above that Dimitrov in view of Jouppi teaches the apparatus in Claim 11 (which is dependent on claim 10), Dimitrov in view of Jouppi necessarily teach the corresponding method.
Regarding claim 27:
Claim 27 is substantially similar to Claim 12, and is therefore rejected for similar reasons, with the following notable differences:
Claim 27 is a method claim instead of an apparatus claim. In showing above that Dimitrov in view of Jouppi teaches the apparatus in Claim 12, Dimitrov in view of Jouppi necessarily teach the corresponding method.
Claims 15 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Dimitrov (US 20190206023 A1) and Greene (US 6646639 B1; from Applicant’s IDS, see attached document for paragraph numbers).
Regarding claim 15:
Dimitrov teaches:
The apparatus of claim 1 (as shown above),
Dimitrov fails to explicitly teach:
wherein to calculate the depth value for each of the first set of pixels, the at least one processor is configured to: calculate an amount of bits for the depth value for each of the first set of pixels.
Greene teaches:
wherein to calculate the depth value for each of the first set of pixels, the at least one processor is configured to: calculate an amount of bits for the depth value for each of the first set of pixels (see Note 15A).
Note 15A: Greene teaches: “In this case, the finest level of the z-pyramid is a z-buffer in which z-values are stored at full precision (e.g., in 32 bits per z-value) so that visibility can be established definitively at each image sample. At other pyramid levels, however, it is not necessary to store z-values at full precision, since culling at those levels is conservative. Thus, at all but the finest pyramid level, it makes sense to store z-values at low precision (e.g., in 12 bits) …” (par. 396-397).
The Examiner likens these features in Greene to the features described in [0064] of the specification of the present application: “In some instances of occlusion culling, the corresponding depth value for each pixel may be stored in a memory or buffer. For example, a certain number of bits (e.g., 16 bits (2 bytes), 24 bits, or 32 bits) may be stored for the depth value of each pixel.”
When the precision of the stored z-value can vary, as taught in Greene, it would be obvious for one of ordinary skill in the art to calculate the amount of bits for the depth value so that the correct amount of bits are read and the correct value is retrieved from memory.
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Greene with Dimitrov. Storing varying precisions of depth values, as in Greene, would benefit the Dimitrov teachings by “conserv[ing] storage and memory bandwidth” (Greene, Paragraph (27)).
Regarding claim 28:
Dimitrov teaches:
The method of claim 19 (as shown above), further comprising: configuring the visibility mask prior to configuring the pattern mask configuration associated with the visibility mask (Dimitrov: All potentially visible geometric primitives are then transmitted to the rasterization stage 660. [0119]; see Note 13A), and
Dimitrov fails to teach:
wherein calculating the depth value for each of the first set of pixels further comprises: calculating an amount of bits for the depth value for each of the first set of pixels.
Greene teaches:
wherein calculating the depth value for each of the first set of pixels further comprises: calculating an amount of bits for the depth value for each of the first set of pixels (see Note 15A).
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Greene with Dimitrov. Storing varying precisions of depth values, as in Greene, would benefit the Dimitrov teachings by “conserv[ing] storage and memory bandwidth” (Greene, Paragraph (27)).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Dimitrov (US 20190206023 A1) in view of Kerr (US 20210124582 A1).
Dimitrov in view of Kerr teaches:
The apparatus of claim 1 (as shown above), wherein the apparatus is a wireless communication device, further comprising at least one of an antenna or a transceiver coupled to the at least one processor (Dimitrov: The PPU 200 may be included in a desktop computer, a laptop computer, a tablet computer, a smart-phone (e.g., a wireless, hand-held device), [0102]), wherein to output the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both, the at least one processor is configured to:
output, via at least one of the antenna or the transceiver (Dimitrov: In one embodiment, two or more GPUs are configured to operate as peers, with one peer able to access data (e.g., surfaces) in local memory of another peer through a high-speed data link (e.g., NVLINK, high-speed data link 150 of FIG. 1E). [0022]), the indication of the depth value for each of the first set of pixels and the coverage information for each of the first set of pixels or the second set of pixels, or both (see Note 18A).
Note 18A: In [0022] above, Dimitrov teaches a high-speed data link between GPUs, and uses NVLink as an example.
Dimitrov transmits both the depth and coverage information (emphasis added): “the ZROP unit 354 updates the depth buffer and transmits a result of the depth test to the raster engine 325.” [0091] and “the coarse raster engine to generate coverage information (e.g., an x,y coverage mask for a tile) for the primitive. The output of the coarse raster engine may be transmitted” [0084].
Because Dimitrov states that the output may be “transmitted”, one of ordinary skill in the art would understand that Dimitrov is using the high-speed data link to transmit the information, even between GPUs if necessary. However, Dimitrov does not explicitly teach that the high-speed data link is a transceiver.
Kerr teaches an “I/O unit 305 is configured to transmit and receive communications (e.g., commands, data, etc.) from a host processor (not shown) over the interconnect 302.” [0134]. Because the I/O unit can both transmit and receive, it is understood to be analogous to a transceiver. Furthermore, Kerr teaches that the interconnect may be via NVLink: “The PPU 300 may be connected to a host processor or other PPUs 300 via one or more high-speed NVLink 310 interconnect.” [0132].
Before the effective filing date of the claimed invention, it would have been obvious to a person having ordinary skill in the art to combine the teachings of Kerr with Dimitrov because Kerr and Dimitrov 1) both refer to using the NVLink high-speed data link to transfer between PPUs and 2) are prior art by the same assignee.
Conclusion
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/VINCENT ALEXANDER PROVIDENCE/Examiner, Art Unit 2617 /KING Y POON/Supervisory Patent Examiner, Art Unit 2617