Prosecution Insights
Last updated: April 19, 2026
Application No. 18/720,945

CURRENT OUTPUT DEVICE, METHOD, APPARATUS AND SYSTEM, AND MEDIUM

Non-Final OA §102
Filed
Jun 17, 2024
Examiner
HILTUNEN, THOMAS J
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Suzhou MetaBrain Intelligent Technology Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
87%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
1003 granted / 1235 resolved
+13.2% vs TC avg
Moderate +6% lift
Without
With
+6.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
30 currently pending
Career history
1265
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
44.4%
+4.4% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
10.9%
-29.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1235 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 9, 13, 16, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang (USPN 10,680,507). With respect to claim 1, Tang discloses, in Figs. 1-5, a current output device (Fig 1 and FIG. 1 (CONTINUED), operational details disclosed in Figs. 2-5), comprising a plurality of single-phase power supply chips (each power stage 108 of Fig. 1), a multi-channel detection module (each PHASE CURRENT SENSE circuit 138 of Fig. 1 with TEMPERATURE SENSE circuit 142), a system control module (148, 152 and 140 of Fig. 1) and a variable current compensation module (116 of Fig. 1), wherein: the multi-channel detection module (138 with 142) is connected to temperature pins (temperature pins output from each 108 to 142, see output of 144 of FIG. 1 (CONTINUED)) and current pins (current sense pins output from each 108 to each 138 of Fig. 1, see output of 150 of FIG. 1 (CONTINUED)) of the plurality of single-phase power supply chips (each 108), and is configured for transmitting current temperature values (output of each 144 is the current temperature of each 108) and current current values (output of each 150 is the current current of each 108) of the plurality of single-phase power supply chips (each 108), and at least one of the plurality of single-phase power supply chips is of a type different from the other single-phase power supply chips (there is no explicitly claimed definition of the chip “type”, type is interpreted as different type “phase” of operation. Each 108 has a different type of operation phase, see Col. 4 lines 20-25. Alternatively, different “type(s)” may be interpreted as different offset/voltage setpoints at which at least one of each 108 is operated, see Col. 5 lines 18-27); one end of the system control module (inputs to 148, 152 and 140) is connected to the multi-channel detection module (each output of 138 and 142), and is configured for obtaining the current temperature values (see step 210 of Fig. 2) and the current current values (see step 200 of Fig. 2 and current balance from 138, see Col. 5 lines 18-27), obtaining constraints based on pre-collected relevant parameters (nominal thresholds, see 220) and adjusting the current current values based on the constraints (the current current values are adjusted based on the nominal values, see 220, furthermore, the current balance and amount of activated stages is adjusted according to the detecting current and temperature, see Col. 5 lines 18-27, 61-67 and Col. 6 lines 1-7), and the variable current compensation module (116) is connected to the other end of the system control module (outputs of 152, 140 and 148 via 140 and 152), and is configured for obtaining an output current value of each single-phase power supply chip (116 obtains which power stage is to be on and how much current each power stage is to provide) based on the current current values (based on the values detected by 140 and 152), and outputting a current of each single-phase power supply chip based on the output current value (116 controls each power stage to control the current output from each power stage. Thus, 116 controls the outputting of a current of each power stage. The controlling is based, at least in part, on the output current as detected by 138, 148, 152 and 140, see Col. 5 lines 54-60, see also Figs. 4-5). With respect to claim 9, a current output method applied to the current output device according to any one of claim 1 (method of operating FIG. 1 and FIG. 1(CONTINUED), further details disclosed in Figs. 2-5), wherein the method comprises: collecting a current temperature value (142 detects are current value for each 108 by detecting the maximum/average temperature of all of 108) and a current current value (138 detects a current current value of each 108) of each single-phase power supply chip transmitted by the multi-channel detection module (each 108), wherein a plurality of single-phase power supply chips are provided (plurality of 108), and at least one of the plurality of single-phase power supply chips is of a type different from the other single-phase power supply chips (there is no explicitly claimed definition of the chip “type”, type is interpreted as different type “phase” of operation. Each 108 has a different type of operation phase, see Col. 4 lines 20-25. Alternatively, different “type(s)” may be interpreted as different offset/voltage setpoints at which at least one of each 108 is operated, see Col. 5 lines 18-27); calling pre-collected relevant parameters of each single-phase power supply chip, wherein the relevant parameters at least comprise a rated temperature value and a rated current value (calling pre-collected nominal temperature and current thresholds wherein the circuit is controlled to operate within a predetermined temperature and current threshold ratio, see 220 of Fig. 3 and Figs 3-5); establishing a constraint based on the relevant parameters (constraint of output current according to determined temperature threshold value, see Figs. 3-5); adjusting the current current value based on the constraint (current threshold incremented/decremented according to the determined temperature threshold value, see Fig. 5); acquiring an output current value of each single-phase power supply chip obtained by the variable current compensation module (116 acquires an output current value for each 108 under the control of 148, 152 and 140); and outputting a current of each single-phase power supply chip based on the output current value (each 108 outputs a current based on the output current value under the control of 116). With respect to claim 13, the current output method according to claim 9, wherein the establishing the constraint based on the relevant parameters comprises: adding up current current values of the plurality of single-phase power supply chip to obtain a total current value (the total current value is obtained by the average current as detected by 148. The average current is determined by adding up the current values detected by 138 and dividing by the total number of detected currents, i.e., the process or averaging. Thus, the total current will be determined, at least in part, by the adding up of detected current values of each 108); and determining the constraint based on the total current value (the constraints are determined based on the total current value, see 200-220 of Fig. 2). With respect to claim 16, claim 16 is rejected for essentially the same reasons as claim 9. Each “module” are the associated elements of the rejection of claim 9 responsible for providing the claimed method steps of claims 9 and 16. With respect to claim 19, a current output system (firmware and microcontroller for providing the operations of 110 of Fig. 1, see, Fig. 4 lines 41-42) comprising: a memory configured for storing a computer program (firmware includes both the computer program for instructing the microcontroller and a non-volatile memory for storing the program); and a processor configured for executing the computer program to implement steps of the current output method according to claim 9 claim 9 (microcontroller which provides the operations of 110 and thus the method of claim 9). With respect to claim 20, a non-transitory computer-readable storage medium (firmware for instructing the microcontroller, see, Fig. 4 lines 41-42, the firmware includes non-volatile memory to store the instructions of the firmware), wherein the non-transitory computer-readable storage medium stores a computer program (program of the firmware) which, when executed by a processor (the microcontroller executes the firmware instructions), implements steps of the current output method according to claim 9 (microcontroller which provides the operations of 110 and thus the method of claim 9). Allowable Subject Matter Claims 2-8, 10-12, 14-15 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas J. Hiltunen whose telephone number is (571)272-5525. The examiner can normally be reached 9:00AM-5:30PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849
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Prosecution Timeline

Jun 17, 2024
Application Filed
Jan 30, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
87%
With Interview (+6.0%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1235 resolved cases by this examiner. Grant probability derived from career allow rate.

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