Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on June 17, 20224.
2. Claims 1-15 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d),which the certified copy has been has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 12/05/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 06/17/2024 are acceptable.
Specification
6. Abstract exceeds 150 word.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Specification page 14 line recites “outputs a third level signal through the output terminal 162” should be “outputs a third level signal through the output terminal 163”.
Specification page 15, line 3 recites “second capacitor 41” should be “second capacitor 42”. Appropriate action is required.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-6 and 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “ a third level signal” in lines 21 and 25 should be “the third level signal”.
Claim 4 recites “a fourth level signal” in line 29 should be “the fourth level signal”.
Claim 12 recites “the clock signal” and “the clock input terminal”. There are insufficient antecedent basis for these claim limitations.
Claims 5-6 dependent on claim 4, thus are also rejected because of their dependency.
Claims 13-14 dependent on claim 12, thus are also rejected because of their dependency.
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Dong “CN108646841” in a view of Xia “CN212381445”.
In re to claim 1 Dong discloses a voltage regulator (Figs. 2-4 shows linear voltage stabilizing circuit) comprising a power supply terminal (terminal at Vin) and an output terminal (terminal at Vout), the voltage regulator being configured to provide a power supply voltage at the power supply terminal (Vin), and the output terminal being configured to connect to a load and to provide an output voltage (Vout), wherein the voltage regulator comprises: an NMOS transistor (MN1: 50) comprising a drain electrode connected to the power supply terminal of the voltage regulator (drain of MN is coupled to Vin terminal ), a gate electrode (gate of MN1: 50), and a source electrode connected to the output terminal of the voltage regulator (source is coupled to Vout); a first regulating circuit comprising: a voltage divider circuit (voltage division 40) connected between the output terminal of the voltage regulator (vout) and ground (ground), the voltage divider circuit (40) being configured to generate a feedback voltage based on the output voltage of the output terminal of the voltage regulator (voltage division 40 is coupled to Vout in order to generate feedback voltage to the op-amp 20) ; an error amplifier (error amplification unit 20 ) comprising a first input terminal configured to provide a reference voltage (+ terminal of error amplification unit 20 is coupled to Vref) , a second input terminal (- terminal) connected to the voltage divider circuit (40), and an output terminal (output of error amplification unit 20 ) connected to the gate electrode of the NMOS transistor (VG1 is connected to MN1:50) ; and a second regulating circuit comprising: a charge pump (charge pump 10) comprising an output terminal connected to the gate electrode (output of charge pump 10 is connected to MN1 :50)
Dong discloses output of the charge pump connected to the gate of electrode but fails having an enable control terminal configured to receive an enable control signal and the charge pump being configured to be selectively turned on based on the enable control signal to regulate the output voltage of the voltage regulator.
Whereas, Xia discloses an LED driving circuit (Figs. 1-4, see parag.14-19) comprising a mode control module 100, an enable signal module generations module 200, drive control module 300, regulation and control module 400 a switch module 500. As shown in figure 2, the drive control module 300 comprises a charge pump, wherein an input end of a charge pump is connected to an output end of the enable signal generation module 200 (EN signal); an output end of the charge pump serves as an output end of the drive control module 300 (VG signal); the charge pump is turned on when the enable signal generation module 200 outputs a high level (equivalent to generating an enable signal), so as to generate a driving signal to control the switch tube 500 to turn on; and the charge pump is turned off when the enable signal generation module 200 outputs a low level, and in this case, the charge pump does not work, such that the switch tube 500 is turned off (equivalent to the charge pump being provided with an enable control end, which is configured to receive an enable control signal), see page 7-9.
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing dated of the claimed invention to have modified the charge pump of Dong with an enable control terminal configured to receive an enable control signal and the charge pump being configured to be selectively turned on based on the enable control signal to regulate the output voltage of the voltage regulator as taught by Xia because by using an enable signal, a charge pump to work based on the enabling signal to generate the driving signal to control the switching tube to conduct; a control module, used for when the enabling signal is effective, based on the difference value of the battery positive electrode voltage and the third reference voltage generating output sink current so as to control the size of the driving signal, thus control the size of the driving signal improve the performance and reliability of the voltage regulator , see abstract.
In re to claim 2, Dong as modified discloses (Figs. 1-4) the charge pump (10) .
Furthermore, Xia disclose a clock input terminal (Figs. 1-2 shows a AND gate is coupled to switch . Examiner noted that a clock signal functions similarly to a high-speed, automatic switch (or pushbutton) that toggles between high (on) and low (off) states at a regular, fixed frequency. Both components are used to control the flow of electricity or data and to coordinate the timing of operations in digital systems, thus equivalent to clock signal) , wherein the charge pump is configured to receive a clock signal through the clock input terminal (charge pump is configured to receive an enable signal EN based on switch input (equivalent to clock signal) ) and to increase the voltage at the gate electrode of the NMOS transistor based on the clock signal upon being turned on, to increase the output voltage of the voltage regulator (NMOS tube N1 is configured to receive the gate voltage VG in order to turn on and off switch N1 which cause increase and decrease the output voltage.)
In re to claim 7, Dong as modified discloses (Figs. 1-4) wherein the second regulating circuit (charge pump 10).
Furthermore, Xia discloses a clock circuit configured to output the clock signal (Figs. 1-2 shows a AND gate is coupled to switch . Examiner noted that a clock signal functions similarly to a high-speed, automatic switch (or pushbutton) that toggles between high (on) and low (off) states at a regular, fixed frequency. Both components are used to control the flow of electricity or data and to coordinate the timing of operations in digital systems, thus equivalent to clock signal) , wherein the charge pump is configured to receive a clock signal through the clock input terminal (charge pump is configured to receive an enable signal EN based on switch input (equivalent to clock signal) ).
In re to claim 8 Dong as modified discloses (Figs. 1-4) wherein the second regulating circuit (charge pump 10):
Furthermore, Xia discloses a hysteresis comparator (hysteresis comparator A) comprising a first input terminal (- terminal) , a second input terminal (+ terminal) and an output terminal (OD/PRO), wherein a first threshold voltage and a second threshold voltage are provided at the first input terminal of the hysteresis comparator (Vbatp , Vref are threshold), the first threshold voltage is less than the second threshold voltage (Vref is less than Vbatp) , the second input terminal of the hysteresis comparator is connected to the output terminal of the voltage regulator (Vabtp is connected to the ouput of N1 via R1 and Vbat) , and the output terminal of the hysteresis comparator is connected to the enable control terminal of the charge pump (OD/Pro is connected to EN signal) ; wherein the hysteresis comparator is configured to generate the output signal based on the output voltage of the voltage regulator, the first threshold voltage and the second threshold voltage, and the output signal serves as the enable control signal of the charge pump (Vbatp and Vref is configured to output EN signal).
Allowable Subject Matter
9. Clams 3 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is objected because the prior art in the record fails to discloses or suggest the voltage regulator including the limitation of “a first switch group comprising a plurality of switches; a second switch group comprising a plurality of switches; a first capacitor, together with the first switch group, being coupled between the power supply terminal of the voltage regulator and the ground, as well as being coupled between the output terminal of the charge pump and the ground; a second capacitor, together with the second switch group, being coupled between the power supply terminal of the voltage regulator and the ground, as well as being coupled between the output terminal of the charge pump and the ground; wherein in response to that the charge pump is turned on and the clock signal is a first level signal, one or more switches in the first and second switch groups are selectively controlled to charge the first capacitor and discharge the second capacitor; and in response to that the charge pump is turned on and the clock signal is a second level signal, one or more switches in the first and second switch groups are selectively controlled to discharge the first capacitor and charge the second capacitor; and wherein the charge pump is turned on in response to the enable control signal being a third level signal; and the charge pump is turned off in response to the enable control signal being a fourth level signal.”
Claim 9 is objected because the prior art in the record fails to discloses or suggest the voltage regulator including the limitation of “the hysteresis comparator is further configured to output a third level signal in response to the output voltage of the voltage regulator being not greater than the first threshold voltage, and to output a fourth level signal in response to the output voltage of the voltage regulator being not less than the second threshold voltage.”
Claim 11 is objected because the prior art in the record fails to discloses or suggest the voltage regulator including the limitation of “a controller configured to obtain information indicating that the output voltage of the voltage regulator will drop at a first time and to provide a third level signal to the enable control terminal at a second time prior to the first time is reached; wherein the charge pump is further configured to be turned on in response to receiving the third level signal, to increase the voltage at the gate electrode, thereby increasing the output voltage of the voltage regulator before the output voltage of the voltage regulator drops.”
Claim 10 is dependent on claim 9, thus is objected because of its dependency.
Claim 15 is dependent on claim 11, thus is objected because of its dependency.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pande “12276993 ” discloses present disclosure relate generally to voltage regulators, and more particularly, to low dropout (LDO) regulators.
Kuttner “9312824” disclose the present invention relates to provide a regulator having a high regulation speed and low noise across a wide frequency range. A pass through device outputs a regulated voltage based on a control signal output by an error amplifier. The control signal is boosted via a regulated boost signal.
Tadeparthy “8248150” discloses relate to a charge pump in a low dropout (LDO) regulator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838