DETAILED ACTION
This action is responsive to the following communications: the Application filed June 18, 2024, and Information Disclosure Statement filed on June 18, 2024.
Claims 1-11 are pending. Claims 1, 7 and 11 are independent.
Information Disclosure Statement
Acknowledged is made of Application’s Information Disclosure Statement (IDS) Form PTO-1449 filed on June 18, 2024. This IDS has been considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over (G. Marchegiani et al. (Nonlinear thermoelectricity with electron-hole symmetric systems)).
Noted: This document is recited in IDS (06/18/2024).
Regarding independent claim 1, Marchegiani et al. discloses Superconducting bipolar thermoelectric memory (1) (see page 11, line 5 discloses: However, this of memory is volatile, i.e.) comprising: - a connection in parallel between a bipolar thermoelectric element (2) and a predetermined resistive load (4) (figure (a) below), and- a current generator (6) arranged to send an injected current (lb) (I, figure (a) below) to the thermoelectric element (2) (C, figure (a) below) and the resistive load (4) (R, figure (a) below, also see i(V) curves of Marchegiani et al.), wherein the thermoelectric element (2) is arranged to be heated by a predetermined thermal gradient (temperature gradient)and to generate corresponding output voltages (VL+, VC) (
PNG
media_image1.png
116
166
media_image1.png
Greyscale
) on the resistive load (4) depending on the sign of the injected current (lb), these output voltages (VL+, VC) corresponding to respective logic states (0, 1) stored by the memory (1).
PNG
media_image2.png
138
366
media_image2.png
Greyscale
Claim 1 recites the provision of a current generator arranged to send an injected current to the thermoelectric element and the resistive load of the volatile thermoelectric memory device during operation, whereas Marchegiani et al. discloses the provision of a voltage signal across the thermoelectric element and the resistive element coupled in parallel e.g. voltage biasing of the superconducting memory device.
It is further noted that the memory device of claim 1 on file, defining a current generator arranged to send an injected current to the thermoelectric element and the resistive load, leaves open the actual electrical connection(s)/coupling of the current generator with respect to the thermoelectric element and the resistive load i.e. does not clearly define a memory device parallel of junction, resistor and current generator.
The effect thereof is that the thermoelectric superconducting memory device of claim 1 can be actively written/erased by itself. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to consider the power supply design option of active current biasing instead of passive voltage biasing and this in particular in case of a thermoelectric volatile memory as suggested by Marchegiani et al in order to assure independent operation of the memory.
Regarding claim 3, Marchegiani et al. disclose the limitation of claim 1.
Marchegiani et al. further disclose wherein the maximum distance between the output voltages (VL+, Vt) decreases by increasing the thermal gradient (see page 3, right-hand column last paragraph – page 4, left-hand column, paragraph 1, and figure 2 and 3)
PNG
media_image3.png
250
366
media_image3.png
Greyscale
Regarding claim 4, Marchegiani et al. disclose the limitation of claim 1.
Marchegiani et al. further discloses wherein the thermoelectric element (2) comprises a junction including a first element (8) made up of a first superconducting material (Superconductor1) coupled to a second element made up of a second superconducting material (Superconductor2), wherein two superconducting gaps of the first and second superconducting materials are not identical (see S-I-Sm junction of Marchegiani, figure 1(a)).
Regarding claim 8, Method for writing a superconducting bipolar thermoelectric memory comprising the steps of:- providing (200) a superconducting memory (1) according to any of the preceding claims and applying a thermal gradient to the superconducting memory (1); - sending (202) an injected current (lb) to the thermoelectric element (2 ) and the resistive load (4), thus causing the generation of the output voltage (VL) on the resistive load (4) having a positive (VL+)or negative (VL) value depending on the sign of the injected current (lb) (see rejection of claim 1).
Regarding claim 7, Marchegiani et al. disclose the limitation of claim 1.
Marchegiani et al. further disclose wherein the thermoelectric element (2) and the load resistor (4) are arranged to be placed (see rejection of claim 1) at a predetermined cryogenic temperature (thermal) to ensure the superconductive state of the thermoelectric element (2), and the current generator (6) (I figure 3) is arranged to be placed at room temperature (obvious superconducting memory circuit feature cooling partition for a low temperature cryogenic device set-up)
Regarding claim 9, Marchegiani et al. disclose the limitation of claim 8.
Marchegiani et al. further disclose the steps of increasing or reducing the injected current (Ib) (I, figure (a) above) so that the output voltage (VL)
PNG
media_image1.png
116
166
media_image1.png
Greyscale
changes (204) its sign, thus changing the state of the superconducting memory (1) (obvious memory operating step when trying to change memory state at a given temperature gradient).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over (G. Marchegiani et al.) in view of Gata Germanese et al. (Spontaneous symmetry breaking-induced thermos pin effect in superconducting tunnel juctions)).
Noted: this document is recited in IDS (06/18/2024).
Regarding claim 5, Marchegiani et al. disclose the limitation of claim 1.
However, Marchegiani et al. are silent with respect to Superconducting memory (1) according to any of the Superconducting memory (1) according to any of the wherein the thermoelectric element (2) comprises a junction including a first (14) and a second (16) superconductor layer separated by an insulator layer (18), the two layers (14) and (16) having the same energy gap, wherein the second superconductor layer (16) interacts with an adjacent ferromagnetic insulator layer (20) and the first superconductor layer (14) is the hot electrode.
Gata et al. disclose Superconducting memory (1) according to any of the Superconducting memory (1) according to any of the wherein the thermoelectric element (2) comprises a junction including a first (14) and a second (16) superconductor layer separated by an insulator layer (18), the two layers (14) and (16) having the same energy gap, wherein the second superconductor layer (16) interacts with an adjacent ferromagnetic insulator layer (20) and the first superconductor layer (14) is the hot electrode (see hybrid S-I-S-FM junction of Gata, page 1, leff-hand column, paragraph 1- page 1, right – hand column, last paragraph and figure 1) .
Since Marchegiani et al. and Gata et al. are both from the same field of endeavor, the purpose disclosed by Gata et al. would have been recognized in the pertinent art of Marchegiani et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Marchegiani et al. to teaching of Gata et al. for purpose of using superconducting bipolar to generate current in memory device.
Allowable Subject Matter
Claims 2 and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowed subject matter:
Regarding claim 2, the prior art made of record and considered to the applicant’s disclosure does not teach the claim limitation of wherein a voltage- current curve (100) of the superconducting memory (1) has a hysteretic shape with non-zero output voltages (VL+, VL) in a respective top (100a) or bottom (100b) part of the curve (100) even in the absence of the injected current lb in combination with other limitation as is recited in the claim.
Regarding claim 6, the prior art made of record and considered to the applicant’s disclosure does not teach the claim limitation of wherein the thermoelectric element (2) comprises a junction including a semiconductor layer (22) put in contact with a superconductor layer (24) which acts as the cold electrode of the superconducting memory (1), the semiconductor layer (22) having has an energy gap comparable with the one of the superconductor layer (24) and the junction further including a metallic top gate (26) and a bottom gate (28) to control the energy gap of the junction and an oxide layer (30) placed between the semiconductor layer (22) and the top and bottom gates (26, 28) in combination with other limitation as is recited in the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH D DINH whose telephone number is (571)270-5375. The examiner can normally be reached Monday to Friday 8:00am 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MINH D DINH/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827