DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 5, 7 and 10-19 is is/are rejected under 35 U.S.C. 103 as being unpatentable over Osako et al. (US 11088614) in view of Mossman et al. (US 9714971).
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With respect to claim 1, fig. 1, 2 and 5 of Osako et al. (US 11088614) discloses an active voltage compensation device for actively compensating for noise occurring in each of two or more high-current paths (140) in a common mode, the active voltage compensation device comprising: a sensing unit (110) including a sensing transformer (L1R1-L1N) to sense a noise current in the common mode in the two or more high-current paths to generate an output signal (VCT) corresponding to the noise current; an amplification unit (131 or OP2) to amplify the output signal of the sensing unit to generate an amplified signal; an amplified signal feedback unit (130 with C1 note: Op2 and Op1 also would serve this purpose as each have feedback to the input of the amplifier) to transmit a feedback signal corresponding to the amplified signal of the amplification unit back to the amplification unit; a compensation unit (120 without C1) including a compensation transformer (L2R1-L2N) configured to generate a compensation voltage in series on the two or more high-current paths (paths at output of compensation transformer i.e. at diodes or VL) based on an output voltage corresponding to the amplified signal to increase an equivalent inductance of the two or more high current paths (140) and suppress noise current wherein: the sensing transformer (110) is configured such that a wire for generating an input voltage of the amplification unit is additionally wound around a common mode (CM) choke (i.e., common mode noise suppressor, see and Col. 6 lines 32-37) around which the two or more high-current paths are wound; the compensation transformer includes a primary side (L2A) connected to an output terminal of the amplification unit (131 or OP2) and a secondary side (L2R, L2s, L2T, LTN) connected in series with the two or more high-current paths (140), and has a structure in which a wire of the primary side and a wire of the secondary side pass through a compensation core (Here: this stipulation is met because all the coils are wound around the same core (see Col. 5 line 63 to Col. 6 line 2) ) or are wound around the core only once (Here: because the language is argued in the alternative the stipulation of the primary side and a wire of the secondary side are wound around the core only once is given no patentable weight because the former stipulation of the primary side and a wire of the secondary side passes through a compensation core is met. ); the compensation voltage is determined based on an output voltage (VL) of the amplification unit (131 or OP2) and a turns ratio of the primary side and the secondary side of the compensation transformer (since the elements of 120 are wrapped around the same core the turns ratio will affect the compensation provided by the coils); and the amplified signal feedback unit (130) comprises at least one passive element (R4), and a value of the at least one passive element is determined based on a turns ratio of the sensing transformer and the compensation transformer, or based on a target voltage gain of the amplification unit (Note: the gain of alpha and beta of 131/132 is based on the value of R4, see Col. 10 lines 37-42) but fails to disclose ; and a malfunction detection unit configured to generate a signal corresponding to an operating state of the amplification unit based on a voltage of at least one node within the amplification unit.
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Mossman et al. (US 9714971) discloses a fault detection circuitry used in operational amplifier configured to generate a signal (38c) corresponding to an operating state of the amplification unit (14 of Mossman) based on a voltage (V+ and V-) of at least one node (+ and -) within the amplification unit (14 of Mossman).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the fault detector of Mossman on each of the operational amplifiers of Osako for the purpose of monitoring the operational amplifiers for proper performance while it is being used such that the circuit can be alerted if and when fault in the operation of the device is detected and therefore protect the remainder of the system by tripping one or more circuit breakers thereby preventing damage to the operational amplifiers and other components within the system.
With respect to claim 2, the combination above produces the active voltage compensation device of claim 1, wherein the amplification unit comprises a first amplification unit (Op2) and a second amplification unit (OP3), wherein the first amplification unit amplifies the output signal of the sensing unit to generate the output voltage, and the second amplification unit is connected to the first amplification unit and generates an output current required for noise compensation.
With respect to claim 5, the combination above produces the active voltage compensation device of claim 1, wherein the two or more high-current paths (140) transmit a high current supplied by a second device (2) to a first device (20), and the amplification unit comprises a non-integrated circuit unit (transistors in 135) and one chip integrated circuit unit (op-amps OP2-Op4), wherein the non-integrated circuit unit is designed according to at least one power system of the first device and the second device, and the one chip integrated circuit unit is independent of power rating specifications of the first device and the second device. (Here, an off the shelf amplifier can be used and bipolar transistors selected according to the optimization principles of the device.)
With respect to claim 7, the combination above produces the active voltage device of claim 6, wherein, according to a design of the non-integrated circuit unit (transistors in 135), the one chip integrated circuit unit (OP amps 2-4) is used for the first device of various power systems. (Here, although the amplifier is used in various power systems, this is understood to be intended use of the integrated circuit unit).
With respect to claim 10, the combination above produces the active voltage compensation device of claim 5, wherein a configuration of the one chip integrated circuit unit (OP amps 2-4) is independent of a turns ratio of the sensing transformer and the compensation transformer (inside 120) and a target voltage gain of the amplification unit (131).
With respect to claim 11, the combination above produces the active voltage compensation device of claim 1, wherein the amplified signal feedback unit (130 and C1) comprises a plurality of resistors (R0 and R3-R16) and a capacitor (Here C1).
With respect to claim 12, the combination above produces the active voltage compensation device of claim 1, wherein: the amplification unit (OP2) comprises a non-integrated circuit part and a one -chip ( Here 134 is integrated) circuit part, and the amplified signal feedback unit (op2 or op1) is disposed in the non-integrated part.
With respect to claim 13, the combination above produces the active voltage compensation device of claim 1, wherein, the amplification unit (131 and 132 or opamp2 and opamp 3) comprises a first amplification unit (131 Osako) and a second amplification unit (132 Osako); and the malfunction detection unit (fig. 1 of Mossman) comprises: a first malfunction detection unit configured to generate a signal corresponding to an operating state of the first amplification unit (malfunction unit on the alpha op amp)/ and a second malfunction detection unit (fig. 1 of Mossman malfunction unit on the beta op amp) configured to generate a signal corresponding to an operating state on the second amplification unit.
With respect to claim 14, the combination above produces the active voltage compensation device of claim 13, wherein the malfunction detection unit (fig. 1 of Mossman) further comprises a malfunction determination unit (26 of Mossman) configured to determine the operating state of the amplification unit (31 and 32 of Osako i.e. 14 of Mossman) and generate a malfunction detection signal (Fault) based on signals respectively generated by the first malfunction detection unit (fig 1of Mossman on alpha 131 of Osako) and the second malfunction detection unit (fig. 1 of Mossman on beta 132 of Osako).
With respect to claim the combination above produces the active voltage compensation device of claim 13, wherein: the first malfunction detection unit (fig. 1 of Mossman on alpha 131 of Osako) is configured to generate the signal (18 of Mossman) corresponding to the operating state of the first amplification unit (131) based on a voltage of at least one node within the first amplification unit (input to 12 of Mossman); and the second malfunction detection unit (fig. 1 of Mossman on beta 132 of Osako) is configured to generate the signal (18 of Mossman of Beta 132 of Osako)corresponding to the operating state of the second amplification unit based on a voltage of at least one node within the second amplification unit (input to 12 of Mossman “from Osako 132”).
With respect to claim 16, the combination above produces the active voltage compensation device of claim 13, wherein the first malfunction detection unit (fig. 1 of Mossman based on 131 of Osako) and the second malfunction detection unit (fig. 1 of Mossman based on 132 of Osako) each comprises a malfunction detection signal output unit (26) configured to output a signal corresponding to the operating state and display (display would be interpreted as putting the fault signal 26b at the control) the signal corresponding to the operating state.
With respect to claim 17, the combination above produces the active voltage compensation device of claim 1, wherein at least a portion of the amplification unit (131 or 132 of Osako i.e 12 of Mossman) and the malfunction detection unit (fig. 1 of Mossman) are embedded in one IC chip (i.e. 10 of Mossman).
With respect to claim 18, the combination above produces the active voltage compensation device of claim 17, wherein the IC chip comprises: a power supply terminal (Vcc i.e. 38d) configured to be connected to a power supply (VCC) that supplies power to the amplification unit (i.e. 12) and the malfunction detection unit (i.e. 26); a reference potential terminal (GND i.e. 38e) configured to be connected to a reference potential (GND) of the amplification unit (12 also is grounded) and the malfunction detection unit (fig.1) ; and an output terminal of the malfunction detection unit (38c is connected to ground via intermediate circuits i.e 32 and 12).
With respect to claim 19, the combination above produces the active voltage compensation device of claim 17, wherein the IC chip comprises a terminal (VCC i.e 38d) for connection to a switch (control 28) for selectively supplying power to the malfunction detection unit (TEST).
Claim(s) 6 is is/are rejected under 35 U.S.C. 103 as being unpatentable over Osako et al. (US 11088614) in view of Mossman et al. (US 9714971).
With respect to claim 6, the combination above produces the active voltage compensation device of claim 5, wherein the non-integrated circuit unit is designed according to power rating of the first device. (Here, bipolar transistors would be selected according to optimization principles of the device.) Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Since the designing according to power rating of the first device is not a result effective variable (i.e. critical) this limitation is deemed routine optimization and therefore obvious.
Claim(s) 8 and 9is is/are rejected under 35 U.S.C. 103 as being unpatentable over Osako et al. (US 11088614) in view of Mossman et al. (US 9714971) in further view of Tsuji (US 6903607).
With respect to claim 8, the combination above of Osako and Mossman produces the active voltage compensation device of claim 5, wherein the one chip integrated circuit unit comprises a first integrated circuit unit (the fault detection (fig. 1 of Mossman) as implemented on the alpha op amp of Osaka ) and a second integrated circuit unit (the fault detection (fig. 1 of Mossman) as implemented on the beta op amp of Osaka ), but fails to explicitly show the details of the transistor 14 of Mossman wherein the second integrated circuit unit comprises a first transistor, a second transistor, and one or more resistors (Here, an operational amplifier as such is made of multiple transistor and resistors).
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Tsuji et al. discloses a typical transistor showing the details of the transistor. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the transistor of Tsuji in the transistor of Mossman for the purpose of showing the details of Mossman and the Tsuji disclosed purpose of reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltage thereof, thus avoiding unnecessary reduction of an S/N ratio.
The resulting circuit would disclose wherein the second integrated circuit unit (the fault detection (fig. 1 of Mossman) as implemented on the beta op amp of Osaka )comprises a first transistor (MP1 of Tsuji), a second transistor (MP2 of Tsuji), and one or more resistors (R1 and R2 of Tsuji).
With respect to claim 9, the combination above of Osaka and Mossman produces the active voltage compensation device of claim 8, wherein the first integrated circuit unit (the fault detection (fig. 1 of Mossman) as implemented on the alpha op amp of Osaka ) but fails to explicitly show comprises one or more transistors. (Here, an operational amplifier as such is made of multiple transistor and resistors).
Tsuji et al. discloses a typical transistor showing the details of the transistor. It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the transistor of Tsuji in the transistor of Mossman for the purpose of showing the details of Mossman and the Tsuji disclosed purpose of reliably prevent voltages applied to the first PMOS transistors from exceeding breakdown voltage thereof, thus avoiding unnecessary reduction of an S/N ratio.
The resulting circuit would disclose wherein the first integrated circuit unit (the fault detection (fig. 1 of Mossman) as implemented on the alpha op amp of Osaka ) comprises a first transistor (MP1 of Tsuji), a second transistor (MP2 of Tsuji), and one or more resistors (R1 and R2 of Tsuji).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2 and 5-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
