Prosecution Insights
Last updated: July 05, 2026
Application No. 18/721,874

ACTIVE VOLTAGE COMPENSATION DEVICE

Non-Final OA §102
Filed
Jun 20, 2024
Priority
Apr 15, 2022 — RE 10-2022-0046883 +1 more
Examiner
ALMO, KHAREEM E
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Em Coretech Inc.
OA Round
3 (Non-Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
624 granted / 714 resolved
+19.4% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
749
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
48.5%
+8.5% vs TC avg
§102
44.8%
+4.8% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 714 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/7/2026 has been entered. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Osako et al. (US 11088614). PNG media_image1.png 433 649 media_image1.png Greyscale PNG media_image2.png 516 632 media_image2.png Greyscale PNG media_image3.png 453 603 media_image3.png Greyscale With respect to claim 1, fig. 1, 2 and 5 of Osako et al. (US 11088614) discloses an active voltage compensation device for actively compensating for noise occurring in each of two or more high-current paths (140) in a common mode, the active voltage compensation device comprising: a sensing unit (110) including a sensing transformer (L1R1-L1N) to sense a noise current in the common mode in the two or more high-current paths to generate an output signal (VCT) corresponding to the noise current; an amplification unit (131 or OP2) to amplify the output signal of the sensing unit to generate an amplified signal; an amplified signal feedback unit (130 with C1 note: Op2 and Op1 also would serve this purpose as each have feedback to the input of the amplifier) to transmit a feedback signal corresponding to the amplified signal of the amplification unit back to the amplification unit; and a compensation unit (120 without C1) including a compensation transformer (L2R1-L2N) configured to generate a compensation voltage in series on the two or more high-current paths (paths at output of compensation transformer i.e. at diodes or VL) based on an output voltage corresponding to the amplified signal to increase an equivalent inductance of the two or more high current paths (140) and suppress noise current , wherein: the sensing transformer (110) is configured such that a wire for generating an input voltage of the amplification unit is additionally wound around a common mode (CM) choke (i.e., common mode noise suppressor, see and Col. 6 lines 32-37) around which the two or more high-current paths are wound; the compensation transformer includes a primary side (L2A) connected to an output terminal of the amplification unit (131 or OP2) and a secondary side (L2R, L2s, L2T, LTN) connected in series with the two or more high-current paths (140), and has a structure in which a wire of the primary side and a wire of the secondary side pass through a compensation core (Here: this stipulation is met because all the coils are wound around the same core (see Col. 5 line 63 to Col. 6 line 2) ) or are wound around the core only once (Here: because the language is argued in the alternative the stipulation of the primary side and a wire of the secondary side are wound around the core only once is given no patentable weight because the former stipulation of the primary side and a wire of the secondary side passes through a compensation core is met. ); the compensation voltage is determined based on an output voltage (VL) of the amplification unit (131 or OP2) and a turns ratio of the primary side and the secondary side of the compensation transformer (since the elements of 120 are wrapped around the same core the turns ratio will affect the compensation provided by the coils); and the amplified signal feedback unit (130) comprises at least one passive element (R4), and a value of the at least one passive element is determined based on a turns ratio of the sensing transformer and the compensation transformer, or based on a target voltage gain of the amplification unit (Note: the gain of alpha and beta of 131/132 is based on the value of R4, see Col. 10 lines 37-42). With respect to claim 2, Osako discloses the active voltage compensation device of claim 1, wherein the amplification unit comprises a first amplification unit (Op2) and a second amplification unit (OP3), wherein the first amplification unit amplifies the output signal of the sensing unit to generate the output voltage, and the second amplification unit is connected to the first amplification unit and generates an output current required for noise compensation. With respect to claim 3, Osako discloses the active voltage compensation device of claim 1, wherein the sensing unit (110) is in a form in which a wire for generating an input voltage of the amplification unit is additionally wound around a common mode (CM) choke around which the two or more high-current paths are wound. With respect to claim 4, Osako discloses the active voltage compensation device of claim 1, wherein the compensation unit (120) is formed such that a wire for outputting the output signal of the amplification unit passes through a core (core of 110), and the two or more high-current paths (140) pass through the core or are wound around the core one or more times. With respect to claim 5, Osako discloses the active voltage compensation device of claim 1, wherein the two or more high-current paths (140) transmit a high current supplied by a second device (2) to a first device (20), and the amplification unit comprises a non-integrated circuit unit (transistors in 135) and one chip integrated circuit unit (op-amps OP2-Op4), wherein the non-integrated circuit unit is designed according to at least one power system of the first device and the second device, and the one chip integrated circuit unit is independent of power rating specifications of the first device and the second device. (Here, an off the shelf amplifier can be used and bipolar transistors selected according to the optimization principles of the device.) With respect to claim 6, Osako discloses the active voltage compensation device of claim 5, wherein the non-integrated circuit unit is designed according to power rating of the first device. (Here, bipolar transistors would be selected according to optimization principles of the device.) With respect to claim 7, Osako discloses the active voltage device of claim 6, wherein, according to a design of the non-integrated circuit unit (transistors in 135), the one chip integrated circuit unit (OP amps 2-4) is used for the first device of various power systems. (Here, although the amplifier is used in various power systems, this is understood to be intended use of the integrated circuit unit). With respect to claim 8, Osako discloses the active voltage compensation device of claim 5, wherein the one chip integrated circuit unit comprises a first integrated circuit unit and a second integrated circuit unit, wherein the second integrated circuit unit comprises a first transistor, a second transistor, and one or more resistors (Here, an operational amplifier as such is made of multiple transistor and resistors). With respect to claim 9, Osako discloses the active voltage compensation device of claim 8, wherein the first integrated circuit unit comprises one or more transistors. (Here, an operational amplifier as such is made of multiple transistor and resistors). With respect to claim 10, Osako discloses the active voltage compensation device of claim 5, wherein a configuration of the one chip integrated circuit unit (OP amps 2-4) is independent of a turns ratio of the sensing transformer and the compensation transformer (inside 120) and a target voltage gain of the amplification unit (131). With respect to claim 11, Osako discloses the active voltage compensation device of claim 1, wherein the amplified signal feedback unit (130 and C1) comprises a plurality of resistors (R0 and R3-R16) and a capacitor (Here C1). With respect to claim 12, Osako discloses the active voltage compensation device of claim 1, wherein: the amplification unit (OP2) comprises a non-integrated circuit part and a one -chip ( Here 134 is integrated) circuit part, and the amplified signal feedback unit (op2 or op1) is disposed in the non-integrated part. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeong et al. (US 20220029548) Nagasawa (US 11843384) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHAREEM E ALMO/Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

Show 2 earlier events
Dec 03, 2025
Response Filed
Feb 18, 2026
Final Rejection mailed — §102
Apr 13, 2026
Examiner Interview Summary
Apr 13, 2026
Applicant Interview (Telephonic)
Apr 16, 2026
Response after Non-Final Action
May 07, 2026
Request for Continued Examination
May 11, 2026
Response after Non-Final Action
May 19, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.1%)
2y 3m (~3m remaining)
Median Time to Grant
High
PTA Risk
Based on 714 resolved cases by this examiner. Grant probability derived from career allowance rate.

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