Prosecution Insights
Last updated: July 17, 2026
Application No. 18/722,165

LIGHT-EMITTING DIODE

Non-Final OA §103
Filed
Jun 20, 2024
Priority
Dec 23, 2021 — RE 10-2021-0186296 +3 more
Examiner
RAHAMAN, SHAHAN UR
Art Unit
Tech Center
Assignee
Seoul Viosys Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
498 granted / 654 resolved
+16.1% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
35 currently pending
Career history
698
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
74.4%
+34.4% vs TC avg
§102
2.6%
-37.4% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 654 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Following is a list of prior arts are considered pertinent to applicant's disclosure, including prior arts not relied upon in the rejection US 20200220049 A1 (OH) US 20110079813 A1 (Yeol) US 20190280178 A1 Claim Objection (Allowable Subject Matter) Claims 7-9 and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-6, 11-13, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over OH in view of Yeol. Regarding Claim 1. OH teaches a light emitting diode [(Fig.1-5 & 10 and para 66-106 )], comprising: a substrate [(21 )]: a first conductivity type semiconductor layer disposed on the substrate: [(23 )] a mesa [(M1, M2 )]disposed on the first conductivity type semiconductor layer, and including an active layer [(25 )] and a second conductivity type semiconductor layer [(27 )]: an ohmic contact layer [(31 )] disposed on the second conductivity type semiconductor layer ohmic contact layer [(33, Fig.3 )] a metal reflection layer [(35a-b, para 92 )]covering the dielectric layer, and electrically connected to the ohmic contact layer through the openings of the dielectric layer: [(Fig.10 & 3 )] a lower insulation layer [(37 )]covering the metal reflection layer, and having an opening exposing the metal reflection layer: [(37b and Fig.10 )] and first and second bump pads disposed over the lower insulation layer, and electrically connected to the first and second conductivity type semiconductor layers, respectively. [(39a-b fig.3 and 10 )] OH does not explicitly show that ohmic contact layer is formed of islands spaced apart from one another However, in the same/related field of endeavor, Yeol teaches that ohmic contact layer is formed of islands spaced apart from one another [(Fig.10 para 101, 24, 97-100 & 119 )] Therefore, in light of above discussion it would have been obvious to one of the ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teaching of the prior arts because such combination would localize the polarization effect when the LED operates, thereby improve reliability of the LED [(Yeol para 97 )] The additional limitations of following claims are taught by OH and/or Yeol as indicated below 2. The light emitting diode of claim 1, wherein: The dielectric layer covers the islands and the second conductivity type semiconductor layer exposed between the islands, and the openings of the dielectric layer exposing the ohmic contact layer are respectively disposed on the islands to partially expose the islands. [(Yeol Fig.11 and 9C )] 3. The light emitting diode of claim 1, wherein each of the islands has a circular shape [(Yeol FIg.6 and para 99 )], a diameter of each of the islands exceeds four times of diameters of the openings of the dielectric layer[(Yeol FIg.10 and OH Fig.10 the openings are small compare to the metal)], and an interval between the islands is equal to or larger than the diameters of the openings. [(Yeol FIg.10)] 4. The light emitting diode of claim 3, wherein: wherein the interval between the islands is smaller than the diameter of the island. [(Yeol FIg.10 and OH Fig.10)] 5. The light emitting diode of claim 1, wherein the lower insulation layer includes a distributed Bragg reflector. [(OH para 95 )] 6. The light emitting diode of claim 1, further comprising: a first pad metal layer disposed on the lower insulation layer, and electrically connected to the first conductivity type semiconductor layer: and a second pad metal layer disposed on the lower insulation layer, and electrically connected to the metal reflection layer through the opening of the lower insulation layer. [(OH Fig.3 )] 11. The light emitting diode of claim 1, further comprising: a rim dielectric layer laterally spaced apart from the dielectric layer and disposed along an edge of the first conductivity type semiconductor layer. [(OH Fig.2-3 and para 102 )] 12. The light emitting diode of claim 11, wherein the rim dielectric layer is formed of a same material as that of the dielectric layer. [(OH Fig.3 #50 )] 13. The light emitting diode of claim 11, wherein the rim dielectric layer is laterally spaced apart from the lower insulation layer. [(OH Fig.3 #50 )] 16. The light emitting diode of claim 1, wherein the ohmic contact layer is formed of a conductive oxide layer. [(OH para 130, 74, 155 )] 17. The light emitting diode of claim 16, wherein the conductive oxide layer is ITO (Indium Tin Oxide). [(OH para 130, 155 )] 18. A light emitting diode, comprising: a first conductivity type semiconductor layer: a mesa disposed on the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer: an ohmic contact layer disposed on the second conductivity type semiconductor layer and formed of islands spaced apart from one another: a dielectric layer covering the ohmic contact layer, and having openings respectively exposing the islands: a metal reflection layer covering the dielectric layer, and electrically connected to the islands through the openings of the dielectric layer: and a lower insulation layer covering the metal reflection layer, and having an opening exposing the metal reflection layer. [(see analysis of claim 1 and Figs 1-5 and 10 of OH )] 19. The light emitting diode of claim 18, wherein the ohmic contact layer is formed of ITO. [(OH para 130, 155 )] 20. The light emitting diode of claim 18, wherein the dielectric layer and the lower insulation layer cover a side surface of the mesa, and partially cover the first conductivity type semiconductor layer exposed around the mesa along an edge of the mesa. [(FIg.3 at the middle )] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahan Rahaman whose telephone number is (571)270-1438. The examiner can normally be reached on 7am - 3:30pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nasser Goodarzi can be reached at telephone number (571) 272-4195. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form. /SHAHAN UR RAHAMAN/Primary Examiner, Art Unit 2426
Read full office action

Prosecution Timeline

Jun 20, 2024
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
89%
With Interview (+12.6%)
2y 10m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 654 resolved cases by this examiner. Grant probability derived from career allowance rate.

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