Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-13 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Clarke et al (US Pub No. 20190042965), hereinafter "Clarke", in view of Friesen (US 8164082), hereinafter "Friesen"].
As per claim 1, Clarke significantly teaches a method for operating a quantum computing element with a network of shuttling lanes having multiple junctions and multiple manipulation zones (the first gate lines 102 and the second gate lines 104 may form a grid [Clarke PP 0019]),
wherein at least one of the qubits is shuttled along the network of the shuttling lanes between steps a) and c) so as to pass at least four different of the junctions (shuttling operations to move electrons to different vacant quantum dot locations (potentially moving through multiple vacant locations before arriving at the desired location) [Clarke pp 0031]).
Clarke does not explicitly teach “wherein the method respectively comprises for a plurality of spin qubits: a) initializing the qubit; b) manipulating the qubit in at least one of the manipulation zones; and c) reading out the qubit;”
However, Friesen, in an analogous art, teaches wherein the method respectively comprises for a plurality of spin qubits (An example is the spin of an electron [Friesen pp 0003]):
a) initializing the qubit (a spin-bus comprising a string of qubits composed of electron spins can be initialized by thermalizing in a DC magnetic field [Friesen pp 0025]);
b) manipulating the qubit in at least one of the manipulation zones (Two-qubit gates are implemented by lowering the electrostatic barrier between the qubits [Friesen pp 0029]); and
c) reading out the qubit (readout sector 35 having one or more qubits selectively coupled to the spin bus by one or more couplings 36 that can be turned on and off electronically, with one or more readout devices 38 coupled to the qubits to provide readout information [Friesen pp 0024]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the quantum dot lattice disclosed by Clarke to incorporate Friesen’s teachings of two-qubit gates implemented by lowering the electrostatic barrier between qubits, in order to improve prospects for scalability (circumvents the need for multiple, local SWAP operations, thus improving the prospects for scalability and fault-tolerance [Friesen 0007]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 2, Clarke does not explicitly teach “wherein steps a) to c) are performed simultaneously for at least some of the qubits.”
However, Friesen, in an analogous art, teaches wherein steps a) to c) are performed simultaneously for at least some of the qubits (the use of a plurality of qubits in the readout sector, as shown in FIG. 1, is advantageous because it enables parallel operation [Friesen pp 0024]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the quantum dot lattice disclosed by Clarke to incorporate Friesen’s teachings of two-qubit gates implemented by lowering the electrostatic barrier between qubits, in order to improve prospects for scalability (circumvents the need for multiple, local SWAP operations, thus improving the prospects for scalability and fault-tolerance [Friesen 0007]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 3, Clarke significantly teaches wherein the method comprises multiple adjacent time intervals, and wherein in each of the time intervals steps a) to c) are performed for a respective set of the qubits (A dynamic scheduler 230 schedules operations to be performed on the quantum processor 260 as specified by the quantum runtime 202 [Clarke pp 0030]).
As per claim 4, Clarke significantly teaches wherein at least temporarily the number of qubits is higher than half the number of the junctions (the adaptive machine configuration controller 240 chooses and configures occupation densities on the physical quantum processor 260. [Clarke pp 0031]).
As per claim 5, Clarke significantly teaches wherein at least some of the qubits are shuttled past the at least one manipulation zone in which they are manipulated in step b) (moving a physical qubit through a lattice [Clarke pp 0039]).
As per claim 6, Clarke significantly teaches wherein at least some of the qubits have a shuttling direction reversed at the at least one manipulation zone in which they are manipulated in step b) (control the potential energy barrier under the first gates ... between adjacent quantum wells [Clarke pp 0016]).
As per claim 7, Clarke significantly teaches wherein at least some of the qubits are successively manipulated in multiple of the manipulation zones, and wherein the respective qubits are shuttled in between these manipulation zones (moving a physical qubit through a lattice [Clarke pp 0039]).
As per claim 8, Clarke does not explicitly teach “wherein for at least some of the qubits the manipulation in the respective step b) is an entanglement with at least one further of the qubits.”
However, Friesen, in an analogous art, teaches wherein for at least some of the qubits the manipulation in the respective step b) is an entanglement with at least one further of the qubits (Two-qubit gates are implemented by lowering the electrostatic barrier between the qubits [Friesen pp 0029]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the quantum dot lattice disclosed by Clarke to incorporate Friesen’s teachings of two-qubit gates implemented by lowering the electrostatic barrier between qubits, in order to improve prospects for scalability (circumvents the need for multiple, local SWAP operations, thus improving the prospects for scalability and fault-tolerance [Friesen 0007]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 9, Clarke significantly teaches wherein the method is a realization of a surface code (qubit lattice [Clarke pp 0038]).
As per claim 10, Clarke significantly teaches a quantum computer comprising: a quantum computing element (a quantum dot device [Clarke PP 0013]) having a network of shuttling lanes with multiple junctions and multiple manipulation zones (the states of the quantum dots (e.g., the spin states) may be manipulated by applying electromagnetic energy to the gates lines [Clarke PP 0017]); and a control installation connected to the quantum computing element and configured for performing a method according to any of the preceding claims (the adaptive machine configuration controller 240. [Clarke PP 0030]).
As per claim 11, Clarke significantly teaches A method for error correction using a quantum computing element with a network of shuttling lanes having multiple X-junctions so as to form multiple network cells, wherein the network further has multiple manipulation zones (the first gate lines 102 and the second gate lines 104 may form a grid [Clarke pp 0019]), wherein the method comprises initializing a respective data qubit in each of the manipulation zones (the states of the quantum dots (e.g., the spin states) may be manipulated by applying electromagnetic energy to the gate lines [Clarke pp 0017]), wherein the method comprises for at least some of the X-junctions of the network:
A1) initializing a respective ancillary qubit in one of the shuttling lanes adjacent to the respective X-junction (shuttling operations to move electrons to different vacant quantum dot locations [Clarke pp 0031]);
A2) successively shuttling the ancillary qubit to the manipulation zones adjacent to the respective X-junction and entangling the ancillary qubit with the data qubits in these manipulation zones (moving a physical qubit through a lattice [Clarke pp 0039]); and
A3) reading out the ancillary qubit (values of data qbits are read and stored in the results 270 [Clarke pp 0045]);
wherein the method subsequently comprises for each of the network cells:
B1) initializing a respective ancillary qubit in one of the shuttling lanes of the respective network cell (shuttling operations to move electrons to different vacant quantum dot locations [Clarke pp 0031]);
B2) successively shuttling the ancillary qubit to the manipulation zones of the respective network cell and entangling the ancillary qubit with the data qubits in these manipulation zones (moving a physical qubit through a lattice [Clarke pp 0039]); and
B3) reading out the ancillary qubit (values of data qbits are read and stored in the results 270 [Clarke pp 0045]);
Clarke does not explicitly teach “wherein the data qubits and the ancillary qubits are spin qubits.”
However, Friesen, in an analogous art, teaches wherein the data qubits and the ancillary qubits are spin qubits (An example is the spin of an electron [Friesen pp 0003]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the quantum dot lattice disclosed by Clarke to incorporate Friesen’s teachings of two-qubit gates implemented by lowering the electrostatic barrier between qubits, in order to improve prospects for scalability (circumvents the need for multiple, local SWAP operations, thus improving the prospects for scalability and fault-tolerance [Friesen 0007]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
As per claim 12, Clarke significantly teaches wherein steps A1) to A3) are performed alternatingly with steps B1) to B3) (A dynamic scheduler 230 schedules operations to be performed on the quantum processor 260 as specified by the quantum runtime 202 [Clarke pp 0030]).
As per claim 13, Clarke does not explicitly teach “wherein steps A1) to A3) are performed simultaneously for all ancillary qubits and/or wherein steps B1) to B3) are performed simultaneously for all ancillary qubits.”
However, Friesen, in an analogous art, teaches wherein steps A1) to A3) are performed simultaneously for all ancillary qubits and/or wherein steps B1) to B3) are performed simultaneously for all ancillary qubits (the use of a plurality of qubits in the readout sector, as shown in FIG. 1, is advantageous because it enables parallel operation [Friesen pp 0024]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the quantum dot lattice disclosed by Clarke to incorporate Friesen’s teachings of two-qubit gates implemented by lowering the electrostatic barrier between qubits, in order to improve prospects for scalability (circumvents the need for multiple, local SWAP operations, thus improving the prospects for scalability and fault-tolerance [Friesen 0007]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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