DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Preliminary Amendments
Applicant’s preliminary amendment filed on June 20, 2024 is acknowledged. Claims 1-10, 13-14, 16-20, and 22-24 are currently pending.
Drawings
The drawings are objected because (1) Figure 3 shows Source Controller connected to gate lines 408 and Gate Controller connected to scan lines 406. It seems that the “Source Controller” and “Gate Controller” should be swapped with each other; (2) Figure 3 shows “404,” “414,” and “416,” which are not disclosed in the text of the specification. It seems that “404” designates controller, but it is unclear what “414” and “416” designate.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. No new matter should be entered. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim(s) 7, 10, and 22 is/are objected to because of the following informalities:
Claim 7, line 8: “plurality of addressable pixel electrodes” should be “the plurality of addressable pixel electrodes”
Claim 7, lines 9-10: “each pixel” should be “each electrode”
Claim 10, line 2: “are fabricated” should be “is fabricated”
Claim 22, lines 1-2: “the first and second high voltage” should be “the first and second high voltages”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-10, 13-14, 16-20, and 22-24 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The terms “a (first/second) low level voltage” in claims 1-2 and 16, “a first low level voltage” or “a second low level voltage” in claims 4-6 and 17-19, “a first high level voltage” or “a second high level voltage” in claims 4-6 and 17-19, “the first and second high voltage” in claim 22, and “the first and second low voltages” in claim 23 are relative terms which render the claim indefinite. The terms “low level,” “high level,” “low,” and “high” for voltage are not defined by the claim, and the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Examiner notes that claims 22 and 23 defines the first and second high voltages and the first and second low voltages in claim 17, and suggests to specify the voltage as recited in claims 22-23.
Dependent claim(s) 2-10 and 13-14 is/are rejected based on rejected claim 1.
Dependent claim(s) 17-20 and 22-24 is/are rejected based on rejected claim 16.
Claim 1 recites the limitation "the addressable pixel electrodes" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. It is suggested to be “the plurality of addressable pixel electrodes.”
Dependent claim(s) 2-10 and 13-14 is/are rejected based on rejected claim 1.
Claim 4 recites the limitation "a second side of the plurality of storage capacitors" in lines 10-11. It is suggested to be “the second side of the plurality of storage capacitors.”
Claim 5 recites the limitation "a second gate pulse" in line 8. It is suggested to be “the second gate pulse.”
Claim 6 recites the limitation "a second side of the storage capacitors" in line 7. It is suggested to be “the second side of the plurality of storage capacitors.”
Claim 16 recites the limitation "the addressable pixel electrodes" in lines 6-7. There is insufficient antecedent basis for this limitation in the claim. It is suggested to be “the plurality of addressable pixel electrodes.”
Claim 16 recites the limitation "the storage capacitors" in line 8. There is insufficient antecedent basis for this limitation in the claim. It is suggested to be “the plurality of storage capacitors.”
Dependent claim(s) 17-20 and 22-24 is/are rejected based on rejected claim 16.
Claim 17 recites the limitation "a second side of the plurality of storage capacitors" in line 7. It is suggested to be “the second side of the plurality of storage capacitors.”
Claim 20 recites the limitation "the addressable pixel electrodes" in lines 4-5, 6-7, 8, and 9-10. There is insufficient antecedent basis for this limitation in the claim. It is suggested to be “the plurality of addressable pixel electrodes” in all places.
Claim 24 recites the limitation "the addressable pixel electrodes" in lines1-2 and 2-3. There is insufficient antecedent basis for this limitation in the claim. It is suggested to be “the plurality of addressable pixel electrodes” in both places.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim(s) 1-10 and 13-14 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over Crounse (US 11,922,893 referred as Crounse’893 or US 12,400,611 referred as Crounse’611 or US 12,664,954 referred as Crounse’954) in view of Bishop (US 2021/0256920).
Regarding claim 1, Crounse recites an electro-optic display, comprising:
a top electrode;
a plurality of thin film transistors (TFTs) each of the plurality of TFTs include a source, a gate, and a drain;
a plurality of storage capacitors;
a backplane comprising a plurality of addressable pixel electrodes, each of the addressable pixel electrodes electrically coupled to the drain of a respective one of the plurality of TFTs and one of the plurality of storage capacitors;
a microfluidic workspace between the top electrode and the backplane;
a plurality of gate lines, the gate of each of the plurality of TFTs electrically coupled to a respective one of the plurality of gate lines,
a plurality of scan lines, the source of each of the plurality of TFTs electrically coupled to a respective one of the plurality of scan lines; and
a controller electrically coupled to the plurality of gate lines, the plurality of scan lines, the top electrode, and the plurality of storage capacitors to provide time-dependent voltages thereto, the controller further configured or programmed to perform top plane switching to drive the electrowetting device by:
driving the top electrode with a first voltage;
driving the plurality of gate lines with a pulsed waveform to open the plurality of TFTs;
driving the plurality of storage capacitors and the plurality of scan lines with a low level voltage for at least one period of the pulsed waveform; and
driving the top electrode with a second voltage (Crounse’893: claims 1, 11; Crounse’611: claim 1; Crounse’954: claim 1).
Crounse (Crounse’893: claim 1; Crounse’611: claim 1; Crounse’954: claim 1) fails to recite an electrowetting device.
However, Bishop teaches TFT based thin film electronics may be used to control the addressing of voltage pulses to an EWOD array by using circuit arrangements very similar to those employed in AM display technologies (¶4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Crounse by substituting the electro-optic display with the AM-EWoD device because they have the very similar circuit arrangements to control the addressing of voltage pulses by TFT electronics in both Am-EWoD and AM display technologies. The substitution would merely be directed to different intended uses and would yield nothing more than predictable result. MPEP2141(III)(B).
Regarding claim 2, Crounse recites wherein driving the plurality of storage capacitors and the plurality of scan lines with a low level voltage for one period of the pulsed waveform returns a voltage level at the plurality of storage capacitors to zero volts and returns a voltage level at the plurality of scan lines to zero volts (Crounse’893: claim 1).
Regarding claim 3, Crounse recites wherein driving the plurality of gate lines with the pulsed waveform to open the plurality of TFTs includes sequentially driving the plurality of gate lines in a first scan direction with the first pulsed waveform and sequentially driving the plurality of gate lines in a reversed scan direction with a second pulsed waveform (Crounse’611: claim 1).
Regarding claim 4, Crounse recites wherein the controller is configured to drive the electrowetting device by
a) providing a first high voltage to the plurality of scan lines and a first low voltage to the top electrode and a second side of the plurality of storage capacitors;
b) providing a first gate pulse sufficient to open the plurality of TFTs;
c) after the first gate pulse, providing a zero voltage to the plurality of scan lines, the top electrode and the second side of the plurality of storage capacitors;
d) providing a second gate pulse sufficient to open the plurality of TFTs;
e) after the second gate pulse, providing a second low voltage to the plurality of scan lines and a second high voltage to the top electrode and a second side of the plurality of storage capacitors; and
f) providing a third gate pulse sufficient to open the plurality of TFTs (Crounse’893: claim 1).
Regarding claim 5, Crounse recites wherein the controller is configured to drive the electrowetting device by
a) providing a first high voltage to the plurality of scan lines and a first low voltage to the top electrode and a second side of the plurality of storage capacitors;
b) providing a first gate pulse sufficient to open the plurality of TFTs;
c) after the first gate pulse, providing a second low voltage to the plurality of scan lines;
d) providing a second gate pulse sufficient to open the plurality of TFTs;
e) after a second gate pulse, providing a second high voltage to the top electrode and the second side of the plurality of storage capacitors; and
f) providing a third gate pulse sufficient to open the TFTs (Crounse’893: claim 11).
Regarding claim 6, Crounse recites wherein the controller is configured to drive the electrowetting device by
a) providing a first high voltage to the plurality of scan lines and a first low voltage to the top electrode and a second side of the plurality of storage capacitors;
b) providing a first gate pulse sufficient to open the TFTs;
c) after the first gate pulse, providing a second high voltage to the top electrode and a second side of the storage capacitors;
d) providing a second gate pulse sufficient to open the TFTs;
e) after the second gate pulse, providing a second low voltage to the scan lines; and
f) providing a third gate pulse sufficient to open the TFTs (Crounse’954: claim 1).
Regarding claim 7, Crounse recites wherein the controller is configured to drive the electrowetting device by
(a) providing a first voltage to the top electrode;
(b) providing a specific voltage to each electrode of the plurality of addressable pixel electrodes in a first sequential order;
(c) providing a specific voltage to each electrode of the plurality of addressable pixel electrodes in a second sequential order, wherein the order of providing specific voltages to plurality of addressable pixel electrodes in the second sequential order is a reverse order of the first sequential order, and wherein each pixel of the plurality of addressable pixel electrodes receives the same specific voltage in both the first sequential order and the second sequential order; and
(d) providing a second voltage different from the first voltage to the top electrode (Crounse’611: claim 1).
Regarding claim 8, Crounse recites wherein the top electrode is light-transmissive (Crounse’893: claims 3, 13; Crounse’611: claim 3; Crounse’954: claim 3).
Regarding claim 9, Crounse recites wherein the top electrode and a second side of the storage capacitor are electrically coupled to a common node (Crounse’893: claims 4, 14).
Regarding claim 10, Crounse recites wherein the plurality of TFTs are fabricated from amorphous silicon (Crounse’893: claims 5, 15; Crounse’611: claim 2; Crounse’954: claim 4).
Regarding claims 13-14, Crounse in view of Bishop recites all limitations of claim 1. Crounse fails to recite wherein the backplane and the top electrode are coated with a hydrophobic material, wherein the hydrophobic material is adjacent the microfluidic workspace (claim 13) or wherein the backplane additionally comprises a dielectric layer between the plurality of addressable pixel electrodes and the hydrophobic material (claim 14).
However, Bishop teaches the backplane and the top electrode are coated with a hydrophobic material (Fig. 1A; ¶27: top hydrophobic layer 107 and bottom hydrophobic layer 110), wherein the hydrophobic material is adjacent the microfluidic workspace (Fig. 1A: the workspace containing the carrier fluid 102 and the droplet 104) or wherein the backplane additionally comprises a dielectric layer (Fig. 1C; ¶28: a dielectric layer 108) between the plurality of addressable pixel electrodes (Fig. 1C; ¶31: pixel 101) and the hydrophobic material (Fig. 1C; ¶27: bottom hydrophobic layer 110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Crounse by incorporating the dielectric and hydrophobic layers as taught by Bishop because the formed structural device is a traditional EWoD device in the prior art. Here, the claimed limitations are obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results. MPEP 2143(I)(A).
Claim(s) 16-20 and 22-23 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over Crounse (Crounse’893 or Crounse’611 or Crounse’954).
Regarding claim 16, Crounse recites a method of driving an electrowetting device comprising:
a top electrode;
a plurality of thin film transistors (TFTs) each of the plurality of TFTs include a source, a gate, and a drain;
a plurality of storage capacitors;
a backplane comprising a plurality of addressable pixel electrodes, each of the addressable pixel electrodes electrically coupled to the drain of a respective one of the plurality of TFTs and one of the storage capacitors;
a microfluidic workspace between the top electrode and the backplane;
a plurality of gate lines, the gate of each of the plurality of TFTs electrically coupled to a respective one of the plurality of gate lines,
a plurality of scan lines, the source of each of the plurality of TFTs electrically coupled to a respective one of the plurality of scan lines; and
a controller electrically coupled to the plurality of gate lines, the plurality of scan lines, the top electrode, and the plurality of storage capacitors to provide time-dependent voltages thereto, the method comprising:
driving the top electrode with a first voltage;
driving the plurality of gate lines with a pulsed waveform to open the plurality of TFTs;
driving the plurality of storage capacitors and the plurality of scan lines with a low level voltage for at least one period of the pulsed waveform; and
driving the top electrode with a second voltage (Crounse’893: claims 1, 11; Crounse’611: claim 1; Crounse’954: claim 1).
Regarding claim 17, Crounse recites further comprising a method of driving (in order):
a) providing a first high voltage to the plurality of scan lines and a first low voltage to the top electrode and a second side of the plurality of storage capacitors;
b) providing a first gate pulse sufficient to open the plurality of TFTs;
c) after the first gate pulse, providing a zero voltage to the plurality of scan lines, the top electrode and a second side of the plurality of storage capacitors;
d) providing a second gate pulse sufficient to open the plurality of TFTs;
e) after the second gate pulse, providing a second low voltage to the plurality of scan lines and a second high voltage to the top electrode and the second side of the plurality of storage capacitors; and
f) providing a third gate pulse sufficient to open the plurality of TFTs (Crounse’893: claim 1).
Regarding claim 18, Crounse recites further comprising a method of driving (in order):
a) providing a first high voltage to the plurality of scan lines and a first low voltage to the top electrode and a second side of the plurality of storage capacitors;
b) providing a first gate pulse sufficient to open the plurality of TFTs;
c) after the first gate pulse, providing a second low voltage to the plurality of scan lines;
d) providing a second gate pulse sufficient to open the plurality of TFTs;
e) after the second gate pulse, providing a second high voltage to the top electrode and the second side of the plurality of storage capacitors; and f) providing a third gate pulse sufficient to open the plurality of TFTs (Crounse’893: claim 11).
Regarding claim 19, Crounse recites further comprising a method of driving (in order):
a) providing a first high voltage to the plurality of scan lines and a first low voltage to the top electrode and a second side of the plurality of storage capacitors;
b) providing a first gate pulse sufficient to open the plurality of TFTs;
c) after the first gate pulse, providing a second high voltage to the top electrode and the second side of the storage capacitors;
d) providing a second gate pulse sufficient to open the plurality of TFTs;
e) after the second gate pulse, providing a second low voltage to the plurality of scan lines; and
f) providing a third gate pulse sufficient to open the plurality of TFTs (Crounse’954: claim 1).
Regarding claim 20, Crounse recites further comprising a method of driving (in order):
(a) providing a first voltage to the top electrode;
(b) providing a specific voltage to each electrode of the array of addressable pixel electrodes in a first sequential order;
(c) providing a specific voltage to each electrode of the array of addressable pixel electrodes in a second sequential order, wherein the order of providing specific voltages to the addressable pixel electrodes in the second sequential order is a reverse order of the first sequential order, and wherein each of the addressable pixel electrodes receives the same specific voltage in both the first sequential order and the second sequential order; and
(d) providing a second voltage different from the first voltage to the top electrode (Crounse’611: claim 1).
Regarding claim 22, Crounse recites wherein the first and second high voltage are +15V (Crounse’893: claim 6).
Regarding claim 23, Crounse recites wherein the first and second high voltage are +15V (Crounse’893: claim 7).
Claim(s) 24 is/are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over Crounse’611 in view of Bishop.
Regarding claim 24, Crounse’611 recites all limitations of claim 19 (Crounse’954: claim 1), but fails to recited wherein at least 100 pixels of the array addressable pixel electrodes have specific voltages different from the majority of the addressable pixel electrodes.
However, Bishop teaches a method of latched transistor driving in AM-EWoD arrays, wherein the electrode of each pixel is connected to a pixel transistor, and the gate of the pixel transistor is connected to a latching circuit, thus switching the pixel transistor gate of each pixel either on or off (¶25). Each pixel transistor may independently be switched to and latched in the desired state (¶46). In another word, Bishop teaches each pixel is individually addressable.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Crounse’611 by adjusting the number of pixels having specific voltages different from the majority of the addressable pixel electrodes because it would obtain a desired pattern of on/off of the individually addressable pixel array (¶25). Here, known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives if the variations are predictable to one of ordinary skill in the art is prima facie obvious. MPEP 2141(III)(F).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CAITLYN M SUN whose telephone number is (571)272-6788. The examiner can normally be reached M-F: 8:30am - 5:30pm.
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/C. SUN/Primary Examiner, Art Unit 1795
