DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1 and 20.
Pending: 1-5 and 20-25.
Canceled: 6-19.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 6/20/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kojima et al., US Patent 8941124 B2; in view of Chen US Patent 8975659 B2.
Re: Independent Claim 1, Kojima discloses an optoelectronic semiconductor device (15, fig. 1b) having a carrier (19, fig. 1B), an optoelectronic semiconductor chip (15, fig. 1b) arranged on the carrier (19, fig. 1B), and a plurality of columns (18a and 18b, fig. 1b), wherein the plurality of columns (18a and 18b, fig. 1b) are arranged on a base surface (contact surface where 19 and 18a/18b, fig. 1b) of the carrier (19, fig. 1B) opposite to the optoelectronic semiconductor chip (15, fig. 1b) and wherein the plurality of columns (18a and 18b, fig. 1b) cause a thermal heat conduction away from the optoelectronic semiconductor chip (15, fig. 1b) and the carrier (19, fig. 1B), wherein the plurality of columns (18a and 18b, fig. 1b), each comprise an end face facing away from the base surface (contact surface where 19 and 18a/18b, fig. 1b) of the carrier (19, fig. 1B), and wherein a polymer (18, fig. 1B) is arranged between the plurality of columns (18a and 18b, fig. 1b), the base surface (contact surface where 19 and 18a/18b, fig. 1b) of the carrier (19, fig. 1B).
Kojima is silent regarding: the metal layer 19 is a carrier Kojima teaches release the heat of semiconductor chip 15 to thermal conductive side of 21 and Kojima did not show an upper side of a substrate (column 3, lines 38-42;”insulating layer 18 and the resin layer 25 and are bonded to pads formed in the mounting substrate”), and the end faces of the plurality of columns (18a and 18b, fig. 1b) and the upper side of the substrate.
Chen discloses carrier (30, fig. 1A) for the LED chip (10, fig. 1A) an upper side of a substrate (20, fig. 1a), and the end faces of the plurality of columns (1012a and 1012b, fig. 1) and the upper side of the substrate (20, fig. 1a).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a carrier for the LED chip since a carrier and substrate can provide a superior heat dissipation.
Re: Claim 2, Kojima and Chen discloses all the limitations of claim 1 on which this claim depends. Kojima further discloses: wherein one or more subsets of the plurality of columns (18a and 18b, fig. 1b) provide an electrical contact of the optoelectronic semiconductor device (15, fig. 1b).
Re: Claim 3, Kojima and Chen discloses all the limitations of claim 1 on which this claim depends. Kojima further discloses: wherein the plurality of columns (18a and 18b, fig. 1b) comprises a metal including copper or a copper-containing alloy (18a/18b part of 21/22 column 3, lines 53-63).
Re: Claim 4, Kojima and Chen discloses all the limitations of claim 1 on which this claim depends. Kojima further discloses: wherein at least one subset of the plurality of columns (18a and 18b, fig. 1b) are arranged equidistantly from one another on the carrier (19, fig. 1B).
Re: Claim 5, Kojima and Chen discloses all the limitations of claim 1 on which this claim depends. Kojima further discloses: wherein the plurality of columns (18a and 18b, fig. 1b) are arranged in distinctly bounded electrically insulated subsets on the carrier (19, fig. 1B).
Claim(s) 20-25 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kojima et al., US Patent 8941124 B2 (Kojima’124);In view of Kojima US PG pub. 20060216920 A1 (Kojima’920).
Re: Independent Claim 20, Kojima’124 discloses a method for producing an optoelectronic semiconductor device (15, fig. 1b), having the following steps: a) providing a carrier (19, fig. 1B); b) applying a photoresist (41, fig. 6c) to a base surface (contact surface where 19 and 18a/18b, fig. 1b) of the carrier (19, fig. 1B); c) structuring the photoresist (41, fig. 6c) using photolithography; d) exposing the base surface (contact surface where 19 and 18a/18b, fig. 1b) of the carrier (19, fig. 1B) by removing an exposed or unexposed area of the photoresist (41, fig. 6c); f) removing the photoresist (41, fig. 6c); g) providing at least one optoelectronic semiconductor chip (15, fig. 1b) arranged on the carrier (19, fig. 1B); h) isolating the carrier (19, fig. 1B); and i) fastening the optoelectronic semiconductor device (15, fig. 1b) on a substrate (column 3, lines 38-42).
Kojima’124 is silent regarding: the copper layer 21/22 are made using e) galvanically growing a plurality of columns (18a and 18b, fig. 1b) on the base surface (contact surface where 19 and 18a/18b, fig. 1b) of the carrier (19, fig. 1B) in the exposed areas of the photoresist (41, fig. 6c).
Kojima’920 discloses the use of galvanically growing method for growing copper column (¶0053).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include galvanically growing method for growing copper since this method can improve electrical performance and provide superior thermal dissipation.
Re: Claim 21, Kojima’124 and Kojima’920 discloses all the limitations of claim 20 on which this claim depends. Kojima’124 further discloses: wherein the optoelectronic semiconductor device (15, fig. 1b) in step i) is fastened using a polymer (18, fig. 1B) on an upper side of the substrate (column 3, lines 38-42).
Re: Claim 22, Kojima’124 and Kojima’920 discloses all the limitations of claim 20 on which this claim depends. Kojima’124 further discloses: wherein the plurality of columns (18a and 18b, fig. 1b) in step e) are each provided with an end cap made of a solder (column 3, lines 38-42; with a bonding agent such as solder).
Re: Claim 23, Kojima’124 and Kojima’920 discloses all the limitations of claim 20 on which this claim depends. Kojima’124 further discloses: wherein the optoelectronic semiconductor device (15, fig. 1b) in step i) is soldered using the end caps on the upper side of the substrate (column 3, lines 38-42; with a bonding agent such as solder).
Re: Claim 24, Kojima’124 and Kojima’920 discloses all the limitations of claim 20 on which this claim depends. Kojima’124 further discloses: wherein a polymer (18, fig. 1B) is provided between the plurality of columns (18a and 18b, fig. 1b), wherein the end caps are present exposed from the polymer (18, fig. 1B).
Re: Claim 25, Kojima’124 and Kojima’920 discloses all the limitations of claim 20 on which this claim depends. Kojima’124 further discloses: wherein after step h), only one column (17, fig. 1b) is arranged on the carrier (19, fig. 1B) of the optoelectronic semiconductor device (15, fig. 1b).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Wang US patent 9362474 B2”) Discloses a light-emitting device (LED) package component includes a carrier wafer. The carrier wafer includes a first through-substrate via (TSV) configured to electrically connecting features on opposite sides of the carrier wafer. A light-emitting device (LED) is bonded onto the carrier wafer. The LED are electrically connected to the first TSV. A conductive thermal interface material (TIM) is located between, and adjoining, the first TSV and the LED.
* (“Lee et al., US Patent 8866376 B2”) discloses a light emitting device (LED) package and a manufacturing method thereof are provided. The LED package includes a circuit board comprising at least one device region, a plurality of electrode regions, at least one first thermal via exposed through upper and lower surfaces of the at least one device region, and a plurality of second thermal vias exposed through upper and lower surfaces of the plurality of electrode regions; at least one first thermal pad bonded to the upper surface of the at least one device region and connected to the first thermal via; at least one LED mounted on the at least one first thermal pad; a plurality of first electrode pads bonded to the upper surface of the electrode region and connected to the second thermal vias; and a plurality of wires to connect the at least one LED with the plurality of first electrode pads.
* (“Tangring et al., US PG pub. 20210408351 A1”) discloses an optoelectronic semiconductor component having an optoelectronic semiconductor chip for emitting electromagnetic radiation. The optoelectronic semiconductor chip may have a first semiconductor layer, a second semiconductor layer, first and second current spreading layers, electrical connection elements and first connection regions. The first current spreading layer is arranged on a side of the first semiconductor layer facing away from the second semiconductor layer. The first current spreading layer is electrically connected to the first semiconductor layer. The electrical connection elements electrically connect the second semiconductor layer to the second current spreading layer. The first connection regions are connected to the first current spreading layer and extend through the second current spreading layer. An area coverage of the first connection regions in a region between adjacent parts of the second current spreading layer is greater than 20% of the area coverage of the second current spreading layer.
* (“Chiou et al., US PG pub. 20090273002 A1”) discloses an LED is presented. A preferred embodiment includes a plurality of thermal vias located through the packaging substrate to effectively transfer heat away from the LED, and are preferably formed along with conductive vias that extend through the packaging substrate. The thermal vias are preferably in the shape of circles or rectangular, and may either be solid or else may encircle and enclose a portion of the packaging substrate.
* (“Tain et al., US PG pub. 20060278885 A1”) discloses a structure of light emitting diode (LED) wafer-level chip scale packaging (WL-CSP) is disclosed. The process of making the same is also provided in this invention. The LED CSP utilizes the through hole metal filling to enhance heat conduction between the LED die and its carrier substrate. The CSP structure is achieved by bonding pre-processed through-hole-filling carrier substrate against the flip-chip LED wafer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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