DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1.
Pending: 1-10.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 6/20/2024 and 7/9/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMAGE SENSOR INCLUDING VERTICAL TRANSFER REGIONS BORDERED BY VERTICAL TRANSFER GATES.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Independent Claim 1 (and dependent claim(s) 2-10), recite(s) the limitation "at least one first photosensitive area" in line 9 and “the second photosensitive area “ in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 3, recite(s) the limitation " the peripheral insulating trench” in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Takahashi US patent 10734419 B2.
Re: Independent Claim 1, Takahashi discloses a plurality of pixels (fig. 1a) formed in and on a semiconductor substrate (102, fig. 1a and 1b), each pixel including:
at least one first photosensitive region (106c, fig. 1b) formed in the semiconductor substrate (102, fig. 1a and 1b), and adapted to collect light in a first range of wavelengths;
a second photosensitive region (106b, fig. 1b) formed in the semiconductor substrate (102, fig. 1a and 1b) in line with said at least one first photosensitive region (106c, fig. 1b), and adapted to collect light in a second range of wavelengths, different from the first range of wavelengths;
at least one charge collection area (118, fig. 1B) disposed on the of the substrate (102, fig. 1a and 1b) opposite to said at least one first photosensitive area (106c, fig. 1b);
a peripheral isolating trench (166, fig. 1b) extending vertically into the semiconductor substrate (102, fig. 1a and 1b), from said side of the second photosensitive area (106b, fig. 1b), and laterally delimiting said at least one first photosensitive area (106c, fig. 1b) and the second photosensitive area (106b, fig. 1b);
at least one transfer region extending from said at least one first photosensitive area (106c, fig. 1b) to said at least one charge collection area (118, fig. 1B); and
at least one transfer gate (126, fig. 1a) extending vertically between said at least one transfer region and the second photosensitive area (106b, fig. 1b), and laterally bordering said at least one transfer region,
wherein each transfer gate (126, fig. 1a) is bordered by intern sidewalls of the peripheral isolating trench (166, fig. 1b) and transfer gate (126, fig. 1a).
Re: Claim 2, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi further discloses: wherein each transfer gate (126, fig. 1a) further includes a first insulating trench (110, fig. 1c) extending into the semiconductor substrate (102, fig. 1a and 1b) from said side of the substrate (102, fig. 1a and 1b) opposite to said at least one first photosensitive area (106c, fig. 1b), and partially entering the thickness of said at least one first photosensitive area (106c, fig. 1b).
Re: Claim 3, Takahashi disclose(s) all the limitations of claim 2 on which this claim depends. Takahashi further discloses: wherein each charge collection area (118, fig. 1B) extends laterally between the peripheral insulating trench (166, fig. 1b) and the or one of the first insulating trench (110, fig. 1c).
Re: Claim 4, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi further discloses: wherein each transfer gate (126, fig. 1a) is surrounded by a second insulating trench (110, fig. 1d) extending vertically into the substrate (102, fig. 1a and 1b) from said side of the substrate (102, fig. 1a and 1b) opposite to said at least one first photosensitive area (106c, fig. 1b).
Re: Claim 5, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi further discloses: wherein each pixel further includes at least one further transfer gate (126, fig. 1a) extending laterally on said side of the substrate (102, fig. 1a and 1b) opposite to said at least one first photosensitive area (106c, fig. 1b) and at least one further charge collection area (118, fig. 1B).
Re: Claim 6, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi further discloses: wherein each pixel includes four first photosensitive area (106c, fig. 1b)s.
Re: Claim 7, Takahashi disclose(s) all the limitations of claim 6 on which this claim depends. Takahashi further discloses: wherein first photosensitive area (106c, fig. 1b)s are isolated from each other by a third insulating trench (144, fig. 1A).
Re: Claim 8, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi further discloses: wherein the second photosensitive area (106b, fig. 1b) is on and in contact with the first photosensitive area (106c, fig. 1b).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 10 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Takahashi US patent 10734419 B2.
Re: Claim 9, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi further discloses: a control circuit (column 10, lines 65-67 and column 11, lines 1-3; “Transfer voltages are applied to TX1 node 302, TX2 node 304, TX3 node 306, and TX4 node 308 respectively electrically coupled to the pixel device gate electrodes 138 of transfer transistors 124 to control the transfer of charge from the photodetectors 106a-d to the first node 312.”) configured to alternately apply, to said at least one transfer gate (126, fig. 1a).
Takahashi is silent regarding: a first potential adapted to block a transfer of charges from said at least one first photosensitive area (106c, fig. 1b) to said at least one charge collection area (118, fig. 1B); and a second potential, different from the first potential, adapted to allow a transfer of charges from said at least one first photosensitive area (106c, fig. 1b) to said at least one charge collection area (118, fig. 1B).
However, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. The device of Takahashi is structurally identical to the Applicant s claimed device. In addition, since the only distinction between the Applicant's claimed device and Takahashi's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Takahashi's device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Takahashi's.
Re: Claim 10, Takahashi disclose(s) all the limitations of claim 1 on which this claim depends. Takahashi is silent regarding: wherein the first photosensitive area (106c, fig. 1b)s of the sensor pixels (fig. 1a) are intended to capture a 2D image, and the second photosensitive area (106b, fig. 1b)s of the sensor pixels (fig. 1a) are intended to capture a depth image.
However, although these limitations have been considered by the Examiner, they pertain to the manner in which the device operates. It has been held that a claim containing a recitation pertaining to the manner of operation is not deemed to patentably distinguish the claimed device from a prior art device that is structurally identical. The device of Takahashi is structurally identical to the Applicant s claimed device. In addition, since the only distinction between the Applicant's claimed device and Takahashi's is recited in functional language, it is incumbent upon the Applicant to demonstrate that Takahashi's device is not capable of operating as claimed. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that such functional distinctions do not confer patentability when compared with prior art devices like Takahashi's.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Wang et al., US Patent 11830954 B2”) Discloses a microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.
* (“Yokgawa US Patent 11843018 B2”) discloses an imaging device includes a first photoelectric conversion region (170) receiving light within a first range of wavelengths, a second photoelectric conversion region (170) receiving light within a second range of wavelengths, and a third photoelectric conversion region (170) receiving light within a third range of wavelengths. At least a portion of a light-receiving surface of the first photoelectric conversion region has a first concave-convex structure (113), and a light-receiving surface of the second photoelectric conversion region has a different structure (111) than the first concave-convex structure.
* (“Ihara US PG pub. 20160043132 A1”) discloses a CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.
* (“Borthakur et al., US PG pub. 20190131333 A1”) discloses a multi-photodiode image pixels may include sub-pixels with differing light sensitivities. Microlenses may be formed over the multi-photodiode image pixels so that light sensitivity of sub-pixels in an outer group of sub-pixels is enhanced. To prevent high angle light incident upon one of the sub-pixels of the image pixel from generating charges in a photosensitive region of another sub-pixel of the image pixel, intra-pixel isolation structures may be formed. Intra-pixel isolation structures may surround, and in some embodiments, overlap the light collecting region of an inner photodiode. When the intra-pixel isolation structures have a different index of refraction than light filtering material formed adjacent to the isolation structures, high angle light incident upon the isolation structures may be reflected back into the sub-pixel it was initially incident upon. Intra-pixel isolation structures may be formed entirely from optically transparent materials or a combination of optically transparent and opaque materials.
* (“Roy US PG pub. 20190237499 A1”) discloses an image sensor includes a semiconductor region, a first doped region disposed over the semiconductor region, a ring shaped well disposed over the first doped region and surrounding parts of the first doped region, a second doped region formed within the ring shaped well and disposed over the first doped region, and a third doped region disposed over the second doped region. The ring shaped well is defined by a conductor surrounded by an insulator. The conductor is connected to a voltage terminal. The third doped region is more heavily doped than the second doped region, which is more heavily doped than the first region, and are all of the same doping type. The first doped region and the second doped region within the ring shaped well, form a potential barrier for controlling transfer of charge carriers from the first doped region to the third doped region.
* (“Lee et al., US PG pub. 20200119082 A1”) discloses an image sensor is provided to include an active region which comprises: a floating diffusion region; a transfer transistor gate region; transistor active regions; and a well-tap region. The transfer transistor gate region may have a diagonal bar shape to isolate the floating diffusion region in a first corner of the active region. The well-tap region may be positioned between the transfer transistor gate region and the transistor active regions, and isolate the transfer transistor gate region from the transistor active regions.
* (“Suler et al., US PG pub. 20200168646 A1”) discloses an integrated imaging device includes a pixel having a trench that extends into the substrate. The trench is coated with an insulator and filled with a stack including a first polysilicon region and a second polysilicon region. The first and second polysilicon regions are separated from each other by a layer of insulating material. The first polysilicon region may form a gate electrode of a vertical transistor and the second polysilicon region may form an electrode of a capacitor.
* (“Mun et al., US PG pub. 20220013551 A1”) discloses disposing trench isolation structure around the perimeter of the pixel transistor region of the pixel cell. The trench isolation structure includes front side (e.g., shallow and deep) trench isolation structure and back side deep trench isolation structure that abut against or contacts the bottom of front side deep trench isolation structure for isolating the pixel transistor channel of the pixel cell's pixel transistor region. The formation and arrangement of the trench isolation structure in the pixel transistor region forms a floating doped well region, containing, for example, a floating diffusion (FD) and source/drains (e.g., (N) doped regions) of the pixel transistors. This floating P-well region aims to reduce junction leakage associated with the floating diffusion region of the pixel cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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