DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1 and 10.
Pending: 1-10.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 6/20/2024 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMAGING DEVICE WITH SURFACE PINNING LAYER FOR SUPPRESSING WHITE SPOTS AND DARK CURRENT, AND ELECTRONIC DEVICE.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "a layer region" in line 6 of claim 2. There is insufficient antecedent basis for this limitation in the claim. in claim 1 “a layer region” already exist is claim 2 “a layer region” same as claim 1 “a layer region” or this is different “a layer region” for example another layer region?
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Shinohara US PG pub. 20120033119 A1.
Re: Independent Claim 1, Shinohara discloses a photoelectric conversion region (23-25, fig. 10A) including a first semiconductor region (24, fig. 10A) containing a first impurity (P+ type, fig. 10A) and a second semiconductor region (23, fig. 10a) containing a second impurity (n-type, fig. 10a); and a layer region (43 and 69, fig. 10a) including at least a first layer (43, fig. 10a) containing a high concentration of the first impurity (P+ type, fig. 10A) and a second layer (69, fig. 10a) made of a predetermined material on a light incident surface side of the photoelectric conversion region (23-25, fig. 10A).
Re: Claim 2, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: a pixel array part (3, fig. 1) including the photoelectric conversion region (23-25, fig. 10A) disposed therein in an array form (as show in figure 1); and a pixel peripheral part (5, fig. 1) including a processing unit (5, fig. 1) that is disposed therein and processes a signal from the pixel array part (3, fig. 1), wherein the pixel peripheral part (5, fig. 1) is provided with a layer region (¶0055; the column signal processing circuit 5 performs signal-processing, such as CDS for removing fixed pattern noise specific to the pixel 2, signal amplification, and A-D conversion, this processing circuit 5 does not include the first layer 43) not including the first layer (43, fig. 10a).
Re: Claim 3, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the layer region (43 and 69, fig. 10a) has an irregular shape (irregular shape such as u shape).
Re: Claim 4, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the layer region (43 and 69, fig. 10a) has a flat shape (flat shape on the side of the photoelectric conversion region 23-25).
Re: Claim 5, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the second layer (69, fig. 10a) is made of silicon oxide (¶0091).
Re: Claim 6, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the layer region (43 and 69, fig. 10a) includes layers made of silicon oxide, aluminum oxide, and tantalum oxide, respectively (¶0091).
Re: Claim 7, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the layer region (43 and 69, fig. 10a) is formed on the first semiconductor region (24, fig. 10A).
Re: Claim 8, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the layer region (43 and 69, fig. 10a) is formed on the second semiconductor region (23, fig. 10a).
Re: Claim 9, Shinohara disclose(s) all the limitations of claim 1 on which this claim depends. Shinohara further discloses: wherein the first impurity (P+ type, fig. 10A) is a P-type impurity and the second impurity (n-type, fig. 10a) is an N-type impurity.
Re: Independent Claim 10, Shinohara discloses an imaging device (PD, fig. 13); and a processing unit (5, fig. 1), the imaging device including a photoelectric conversion region (23-25, fig. 10A) including a first semiconductor region (24, fig. 10A) containing a first impurity (P+ type, fig. 10A) and a second semiconductor region (23, fig. 10a) containing a second impurity (n-type, fig. 10a), the imaging device further including a layer region (43 and 69, fig. 10a) including at least a first layer (43, fig. 10a) containing a high concentration of the first impurity (P+ type, fig. 10A) and a second layer (69, fig. 10a) made of a predetermined material on a light incident surface side of the photoelectric conversion region (23-25, fig. 10A), and the processing unit being configured to process a signal from the imaging device (¶0055-¶0057).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Tatani et al., US PG pub. 20090256226 A1”) Discloses a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.
* (“Shinohara US PG pub. 20110187911 A1”) discloses a solid-state imaging device is provided, which includes a pixel region in which pixels including a photoelectric conversion section and a plurality of pixel transistors are arranged. In the solid-state imaging device, a transfer transistor of the pixel transistors includes: a transfer gate electrode extended in a surface of the substrate formed on the surface of a semiconductor substrate; and a transfer gate electrode buried in the substrate which is electrically insulated from the transfer gate electrode extended in a surface of the substrate and is embedded in the inside of the semiconductor substrate in the vertical direction through the transfer gate electrode extended in a surface of the substrate.
* (“Ikeda US PG pub 20150015758 A1”) discloses an image sensor including a photoelectric conversion unit for converting a received light into an electric charge; a semiconductor substrate including the photoelectric conversion unit; and a plurality of areas each having a refractive index different from a refractive index of the semiconductor substrate formed between a surface of the semiconductor substrate on which light is incident and the photoelectric conversion unit. Also, provided are an apparatus and a method of producing the image sensor, and an electronic device including the image sensor.
* (“Moriwaki US PG pub. 20210126040 A1”) discloses imaging device includes a photoelectric conversion unit in which a first electrode, a photoelectric conversion layer, and a second electrode are stacked. In the imaging device, an inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer. The inorganic oxide semiconductor material layer contains zinc (Zn) atoms and tin (Sn) atoms, and, when expressed by Zn.sub.aSn.sub.bO.sub.c, satisfies the following conditions: a+b+c=1.00, and b>a.
* (“Miyanami US patent 9153612 B2”) discloses a solid-state imaging device includes a plurality of photoelectric conversion portions each provided to correspond to each of a plurality of pixels in a semiconductor substrate and receiving incident light through a light sensing surface, and a pixel separation portion that is embedded into a trench provided on a side portion of the photoelectric conversion portion and electrically separates the plurality of pixels in a side of an incident surface of the semiconductor substrate into which the incident light enters. The pixel separation portion is formed by an insulation material which absorbs the incident light entering the light sensing surface.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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