DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 3 is objected to because of the following informalities: Claim 3 is dependent on a cancelled claim (claim 2), which is improper. The examiner will treat claim 3 dependency to be on claim 1 for the purpose of examination. Appropriate correction is required.
Claim 12 is objected to because of the following informalities: Claim 12 is dependent on a cancelled claim (claim 11) which is improper. The examiner will treat claim 12 dependency to be on claim 1 for the purpose of examination. Appropriate correction is required.
Claim 14 recites the limitation "the microcontroller" in line 1 should be -- a microcontroller--.
Claim 32 is objected to because of the following informalities: Claim 32 is dependent on a cancelled claim (claim 29) which is improper. The examiner will treat claim 32 dependency to be on claim 1 for the purpose of examination. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 12-15, 18-20, 26-27, 61-62, 64 are rejected under 35 U.S.C. 102a1 as being anticipated by US Patent Application Publication to Huang 2022/0365274US.
In terms of Claim 1, Huang teaches an optical engine (Figure 1a) comprising: an optically transparent substrate (Figure 1a: layer 116 having middle portion 120 which is a substrate that can transmit optical signals which means it’s optically transparent ([0040]) having a first major surface and an opposed second opposed major surface; and an optoelectronic element Figure 1a: 128) configured to emit or receive light through the optically transparent substrate ([0040]); and an associated electrical component (Figure 1a: 130 or 144/146 or all three [0042]) in electrical communication with the optoelectronic element ([0042]) configured to deliver or receive electrical signals to or from the optoelectronic element ([0042]), wherein the first major surface comprises a first surface coating layer (Figure 1a: see 1st major surface having coating 140 made up several metal layers and dielectric within 142 and 148), and wherein the second major surface comprises a second surface coating layer (Figure 1a: see 2nd major surface having coating 114/112 made up several metal layers and dielectric within 114 and 112 such as 114a-b and 112a-b).
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As for Claim 3, Huang teaches the device of Claim 1, wherein associated electrical component (Figure 1a: 130/140/146) comprises a plurality of associated electrical components (130/144/146; [0042]) that are mounted on the first major surface of the optically transparent substrate (Figure 1a: 130/144/146 are mounted on the top of the 1st major surface as shown in Figure 1a above), and the optoelectronic element (Figure 1a: 128) is mounted on the second major surface of the optically transparent substrate (Figure 1a: 128 is mounted over or on top of the bottom surface of 116 as shown above in Figure 1a).
As for Claim 12, Huang teaches the device of Claim 1, wherein the first surface coating layer (Figure 1a: 140) comprises a first surface first metal layer (Figure 1a; metal layer in 147 such as 148; [0078]) disposed on the first major surface of the optically transparent substrate (Figure 1a: 140 and 147 is located on the first major surface of substrate 116/120 as shown above), a first surface first dielectric layer disposed on the first surface first metal layer (Figure 1a: 142; [0042]), a first surface second metal layer disposed on the first surface first dielectric layer (Figure 1a: 142 contain metal traces wherein the metal trace layer is on a portion of 142), and a first surface second dielectric layer (Figure 1a: 145 which is an epoxy layer [0044], wherein epoxy is a known dielectric) disposed on the first surface second metal layer (Figure 1a: 145 is dispose on the metal layer pattern within 142).
As for Claim 13, Huang teaches the device of Claim 12, wherein the first surface first metal layer (147) is a first surface redistribution layer (147 qualifies as a redistribution layer because it contains a dielectric and metal layers to distribute electrical signals to the chips 144/146) that comprises a plurality of first surface contact pads ([0073] wherein 148 is coupled to contact pads).
As for Claim 14, Huang teaches the device of Claim 13, wherein a microcontroller (130) is electrically connected to the first surface contact pads ([0073]).
As for Claim 15, Huang teaches the device of Claim 12, further comprising a first surface via (Figure 3: 123 [0062] or Figure 1a: 116b; [0039]) that electrically connects a portion of the first surface first metal layer (148) with a portion of the first surface second metal layer (Figure 1a: 116b connects to 148 which supplies electrical signal to metal trace in 142 [0049]).
As for Claim 18, Huang teaches the device of Claim 1, wherein the second surface coating layer comprises alternating metal and dielectric layers (See 114 and 112 which alternating metal/dielectric layers).
As for Claim 19, Huang teaches the device of Claim 18, wherein the second surface coating layer (Figure 1a: 114/112) comprises a second surface first metal layer (112b [0087]), a second surface first dielectric layer situated on the second surface first metal layer (Figure 1a: a portion of 112a is located on top of different layers of 112b), a second surface second metal layer (Figure 1a: 114b [0086]) situated on the second surface first dielectric layer (Figure 1a: 114b is located on top of 112a), and a second surface second dielectric layer (Figure 1a: 114a) situated on the second surface second metal layer (Figure 1a: a portion sits on varying layers of 114b metal layers).
As for Claim 20, Huang teaches the device of Claim 19, wherein the second surface first metal layer (114b) is a second surface redistribution layer that comprises a plurality of second surface contact pads (Figure 1a: bottom most 114b of 114 functions as a RDL [0039] wherein bottom most portion of 114b is coupled to 115; 115 contains a bump and a structure located below the bump as shown in Figure 5e which the examiner considers as a contact pad, further the layer of 114 that make contacts with 115 can also be consider a contact pad by the examiner).
As for Claim 26, Huang teaches the device of Claim 1, further comprising a mechanical guard mounted to the first major surface (Figure 1a: 190; [0041]).
As for Claim 27, Huang teaches the device of Claim 1, wherein an uppermost surface of the mechanical guard (Figure 1a: top surface of 190) is spaced from the first major surface (Figure 1a: top surface of 190 and top surface of 116/120) in a transverse direction a greater distance than an uppermost surface of any of the passive components (Figure 1a: see 190 has a height higher than 140), and the first and second major surfaces are opposite each other along the transverse direction (Figure 1a: top and bottom surface of 116/120).
As for Claim 61, Huang teaches the device of Claim 1, wherein the optoelectronic element and the electrical component are configured to be mounted on the second major surface of the optically transparent substrate (Figure 1a: 130 and 128 is on or over the bottom surface of the substrate 116).
As for Claim 62, Huang teaches the device of Claim 1, wherein the optoelectronic element is a photonic integrated circuit (128).
As for Claim 64, Huang teaches the device of Claim 3, wherein the electrical components comprise a microcontroller (130 [0045]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent Application Publication to Kim 2022/0165698.
In regards to Claims 16 and 21, Huang teaches the device of claim 12 and claim 19, wherein the first coating and second coating layers are redistribution layer to distribute electrical signals (Figure 1a: see 140 and 112/114).
Huang does not teach wherein the first surface of metal layer has a plurality of degassing openings that serve no electrical function and are configured to reduce stress in the first surface coating layer; and wherein the second surface second metal layer has a plurality of degassing openings that serve no electrical function and are configured to reduce stress in the first surface coating layer.
Kim teaches a coating layer that functions as distribution layer (Figures 1 and 2b: 110 having layers 112 and 114) that contains metal (112/113) having gaps or holes (118) that function as degassing openings ([0022]); that serve no electrical function and are configured to reduce stress in the first surface coating layer ([0033] teaches openings 118 can distribute the stress and reduce stress build up). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to create degas openings in between the various metal trace layers of 140 and 112//114 in order to distribute the stress and reduce localize stress building up in the distribution layer due temperature variance during operations of transmitting electrical signals. This provides mechanical and thermal stability to the device and increases its durability.
Claims 22-23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang / Kim as applied to claim 21 above, and further in view of US Patent Application Publication to Williams 2018/0341164US.
In regards to Claim 22-23 and 25, Huang / Kim teaches the device of claim 21 wherein the contact pads are each configured to mechanically and electrically attach to a respective solder (Figure 1a: 109 and 119 and 148/147 and 115).
Huang and Kim do not teach wherein the plurality of second surface contact pads comprises differential pair contact pads at a first end of a coplanar transmission line and second surface component contact pads at an opposed second end of the coplanar transmission line.
Williams does teach a photonic circuit (Figure 5) having contact pads (131/132) comprises differential pair contact pads (Figure 5: 131/132; [0073]) at a first end of a coplanar transmission line and second surface component contact pads at an opposed second end of the coplanar transmission line (Figure 5: 131/132 on the left side and right side wherein the transmission lines end). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the contact pads of 148 or the contact pads at 119 to be configured as a pair of differential pair contact pads because the pair allows multiple drive of 2 signals per pair which increase the electrical output and switching functions of each distribution channels. This allows the EIC and PIC to perform faster switching and enables the PIC to operate at faster bandwidths and processing functions.
Huang / Kim and Williams do not teach wherein a maximum cross-sectional dimension of the differential pair contact pad is larger than that of the second surface component contact pad. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the size of the contact pad to be larger relative to second surface component contact pad in order to maximize electrical contact. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Huang / Kim / Williams as applied to claim 22 above, and further in view of US Patent Application Publication to Lee 2022/0021179US.
In regards to Claim 24, Huang / Kim and Williams teaches the device of claim 22, wherein Huang teaches the second surface component contact pad (Figure 1a: 115 is attached to electrically via the top to 114b and via the bottom to a layer that connects to 112b) is configured to mechanically and electrically attach to a bump (Figure 1a: both layer 114b and the electrical layer below 115 is coupled to bump 115).
Huang / Kim / and Williams does not teach wherein the bumps are attached have a stud bump configuration.
Lee teaches and electrical interconnect within a PIC circuit having gold stud bumps as connections means ([0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the connections bumps at 109, 148 and 115 to have a gold stud bump configuration. Golden stud bumps provide good conductive since gold is a known to be an excellent conductor. This reduces the electrical loss to circuit and allows the circuit to run cooler due to less heat from electrical loss.
Claims 31 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent Application Publication to Dietrich 2019/0258175US.
In regards to claims 31 and 32, Huang teaches the device of claim 1.
Huang does not teach wherein device comprise of a lens array having a raised ring having a bottom surface and the bottom surface of the raised ring extends in the transverse direction than any portion of the individual lens; and wherein the lens array is attached to the first major surface of the optically transparent substrate with a sealing adhesive to form an enclosed volume surrounding the individual lenses.
Dietrich does teach a photonic circuit that can contain an array of beam-shaping components 105 ([0182]) wherein the beam shaping component can be a lens (Figure 3a: 40; [0160] and [0198]) having a raised ring (tip of 40) having a bottom surface (51) and the bottom surface (bottom surface of 51) of the raised ring extends in the transverse direction than any portion of the individual lens (Figure 3: 50 extends further than the 40). The structure of 51 severs as a spacing adjust the focal and collimating distance to the photonic substrate 10); and wherein the lens array is attached to the first major surface of the optically transparent substrate (Figure 3a: 10 and 40) with a sealing adhesive to form an enclosed volume surrounding the individual lenses (Figure 22: 52 cures using UV and temperature [0165] as it cures 52 functions as adhesive that hardens and sticks to the lens substrate as shown in Figure 22). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the PIC 128 to include a lens array with a bottom portion similar to 51 and adhering encapsulant over the lens similar to 52 of Dietrich. The modification of to include a bottom portion 51 that extends further than the lens in order to optimize the focal distant of light. This reduces insertion loss into the PIC 128, further the modification of an encapsulant layer 52 will also reduce optical loss due to reflection (Dietrich’s [0165]).
Claim 34 is rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent Application Publication to Nowell 2022/0225537US.
In regards to Claim 34, Huang teaches the optical engine of claim 1.
Huang does not teach wherein the photonic circuit is cooled using immersion cooling.
Nowell does teach optical components and electrical circuits can be cooled using immersion cooling ([0022]; Figures 1 and 2). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the device of Huang to be cooled using immersion cooling. This allows the device to function at a cooler temperature thus increasing its durability over time.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent Application Publication to Lee 2022/0021179US.
In regards to claim 35, Huang teaches the optical engine of claim 1.
Huang does not teach wherein a mechanical stud bump is used to help mount the optoelectronic element to second major surface of the optical transparent substrate.
Lee teaches optical components or photonic dies such a laser die can be interconnected with another substrate or components using stud bumps ([0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of 128 to be attached to substrate 120 using stud bumps because stud bumps are known as effective conducting structures since it is made of gold and can also perform the mechanical function of attachment. This allows the device bump to operate at a lower temperature due to less electrical loss.
Huang and Lee do not teach wherein the optoelectronic element is mounted to second major surface.
The examiner considers the orientation of the 128 on located on the 1st major surface, on the top 2nd major surface or somewhere in the middle to be an obvious modification because rearrangement of parts has been held by the courts that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because the optical component 128 functionality has not been changed. It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify the location of 128 so it can be either closer to electrical contact lines of 140 or 114 which reduces operational cross talk and reduce operational heat during operation. One can route light via the waveguide to 128 be changing the shape of the waveguide or the location of waveguide to correlate to the new location of the optical element.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent Application Publication to Mia 2016/0131861US.
In regards to Claim 36, Huang teaches the device of claim 1, further comprising a plurality of electrically conductive through vias (Figure 1a: 116b) that extend from the first major surface to the second major surface (Figure 1a: 116b extends from the top to bottom of substrate portion 120/116).
Huang does not teach wherein at least one the plurality of electrically conductive through via is hermetically seal such that no undesirable contaminants can propagate through the substrate.
Mia does teach wherein at least one the plurality of electrically conductive through via is hermetically seal ([0047] using sealing ring to seal the via opening) such that no undesirable contaminants can propagate through the substrate ([0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to include seal at the ends of the via 116b in order to prevent unwanted contaminants into the via due to seal being hermetic ([0047]).
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent to Ren 10,791,629US.
In regards to Claim 43, Huang teaches the device of claim 1.
Huang does not teach the electrical signal are electrical signals that travel at data transfer rates equal to or greater than approximately 56 gigabit per second while producing no more than 6% at worst-case multi active cross talk.
Ren teaches wherein the device contains signal pairs of TX and RX (Column 4, lines 25-50) use to transmit data. Ren further indicates in order to achieve speeds of up to 400 gigabit which is higher than 56 gigabit one would need 8 lanes that operate at 53.125 gigabits per second (Column 1, lines 25-40) while maintaining low cross talk.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device Huang wherein signals are transmitted in pairs Tx and Rx in eight separate lanes of transmission in order to achieve high bandwidth for large data transfer.
Huang and Ren do not teach 6% at worst-case multi active cross talk. However, cross talking is a byproduct of the spacing between the electrical lines such as the ones in 140 and 112/114. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the spacings of the electrical traces within 140 and 112/114 in order to prevent electrical crosstalk or noise in the chip. Further other components that use electrical signals such as PIC 128 and EIC 130 can also be modified to have sufficient spacing in its electrical interconnect to each other to avoid unwanted crosstalk. The courts have held that such a modification would have involved a mere change in the size of the component. A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claims 60 are rejected under 35 U.S.C. 103 as being unpatentable over Huang / Kim as applied to claim 16 above, and further in view of US Patent Application Publication to Wickersham 2021/0358021.
In regards to Claim 60, Huang / Kim teaches the device of claim 1.
Huang and Kim do not teach wherein the device is configured to operate in salt spray or salt fog.
Wickersham teaches and electronic circuit board coated Parylene HT [0038] will provide natural corrosive resistant to salt spray or salt fog [0038]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang/Kim to be able to tolerate operation in a salt spray or salt fog environment such as cars operating in on salt treated roads during the winter or near ocean/beach fronts area. This modification allows the device to be used in salt harsh environments.
Claim 63 is rejected under 35 U.S.C. 103 as being unpatentable over the US Patent Application Publication to Huang 2022/0365274US in view of the US Patent to Welch 7,734,191US.
In regards to claim 63, Huang teaches the device of claim 62.
Huang does not teach wherein the PIC circuits has only transmitting capabilities.
Welch teaches a photonic circuit (Figure 5a: 401c wherein the circuit only functions as TxPIC or a transmitting PIC circuit; Column 12, lines 20-35). It would have been obvious to one of ordinary skill in the art to modify the PIC circuit 128 to have a singular function of transmitting for the purpose of scaling the transmission side of the optical network. Further by only having transmitting capabilities the receiver side can be removed to reduce operation power, reduce cost, or to use the spacing for more transmitters in application wherein receivers are not needed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent to Moore teaches optical circuits with bump mounting on are substrate 5,120,678US.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 5712722397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HOANG Q TRAN/ Examiner, Art Unit 2874
/UYEN CHAU N LE/ Supervisory Patent Examiner, Art Unit 2874
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