DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Preliminary Amendment
Acknowledgement is made of the preliminary amendment filed on June 21, 2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 21, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figure 1 is objected to as it contains blank boxes lacking descriptive labels. The drawings should be amended to include labels showing each boxes function in the circuit. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Examination Notice
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Norling (US 2014/0091643 A1) in view of Holmes (US 3,921,035).
With regard to claim 1, Norling teaches a method for checking the turn-off capability of an electronic switch (2 – Fig. 1) in the form of a MOSFET ([0019] lines 1-9), said electronic switch (2 – Fig. 1) being used as an interrupter switch (implicit) between a voltage supply (+VL, GND – Fig. 1) and a control device (Z – Fig. 1), comprising:
turning on the MOSFET (2 – Fig. 1) during operation as intended ([0022] lines 1-4),
operating the MOSFET (2 – Fig. 1) in the linear region ([0003] lines 8-10),
reducing the gate-source voltage (VGS – Fig. 4) of the MOSFET (2 – Fig. 1) by a predefined value (from VDRIVE to 0V in t1, see Fig. 4) until a predefined threshold value (0V, see Fig. 4) is reached,
after the threshold value (0V, see Fig. 4) has been reached, increasing the gate-source voltage to a previous value (from OV to VDRIVE in t8, see Fig. 4) for turning on the MOSFET (2 – Fig. 1), and
ascertaining whether the drain-source voltage (VDS – Fig. 4) of the MOSFET (2 – Fig. 1) increases as the gate-source voltage (VGS – Fig. 4) is reduced (see profile in Fig. 4).
Norling does not teach an electronic fuse.
Holmes teaches electronic switch is an electronic fuse (col. 4, lines 30-33).
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the electronic switch of Norling, to have an electronic fuse, as taught by Meyer, since it is well known in the art that the electronic switch is an electronic fuse; and in order to provide fast response time, resettable, compact size that can be integrated into circuit, and also provide more accurate circuit protection compared to traditional fuses.
With regard to claim 2, Norling and Holmes teach all the limitations of claim 1, and Norling further teaches the MOSFET (2 – Fig. 1) is controlled and checked by a control and diagnosis circuit (5 – Fig. 1; Fig. 3) controlled by a control unit (53 – Fig. 3).
With regard to claim 3, Norling and Holmes teach all the limitations of claim 1, and Norling further teaches the gate-source voltage (VGS – Fig. 4) is reduced in time ranges in which the control device (Z – Fig. 1) does not have a high current demand (see ID profile in Fig. 4).
With regard to claim 4, Norling and Holmes teach all the limitations of claim 2, and Norling further teaches the gate-source voltage (VGS – Fig. 4) is reduced in time ranges in which the control device (Z – Fig. 1) does not have a high current demand (see ID profile in Fig. 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892.
Djelassi-Tscheck (US 2023/0411947 A1) teaches an electronic switch with a load current path, which is switched between an output node and a supply node and is designed to connect or disconnect the output node to or from the supply node in accordance with a control signal. The circuit further comprises a control circuit which is designed to generate the control signal based on an input signal, and a current monitoring circuit which is designed to receive a current measurement signal that represents the load current flowing through the load current path, and to generate a protective signal, based on the current measurement signal, which indicates whether the output node should be disconnected from the supply node. The circuit further comprises a reverse current detection circuit, which is designed to detect that the load current is flowing in the reverse direction, namely from the output node to the supply node. The control circuit is designed to work at least in a normal mode and in an idle mode, wherein the control circuit switches from the normal mode into the idle mode if at least the following idle-mode conditions are met: the load current is below a current threshold; the electronic switch is switched on; and the reverse current detection circuit does not detect a load current in the reverse direction.
Kessler (US 2025/0052815 A1) teaches a circuit arrangement for checking the cutout ability of an electronic fuse used as an interrupter, a first electronic switch, between a power supply and a control device. A second electronic switch is connected in parallel with the first switch has a lower current-carrying capacity than the first switch and is configured, when conductive, to generate a lower voltage drop across its load path than the first switch at the same current as the first switch. The first and the second switches are actuated by a control and diagnostic circuit configured to check the cutout ability of the first switch acting as a fuse when the second switch is switched on, and to check the voltage drop across the two switches and, upon a reduction in the voltage when the second switch is on and the first switch is off, to conclude that the switches are functioning correctly.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/N.B./Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838