Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/24/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Page 9, para [0048], line 4 recites “block 308 is coupled to driver block 318” should be “block 330 is coupled to driver block 318”
Page 11, Para [0060], line 8 recites “Output terminal 412” should be “Output terminal 512”
Page 15-16, Para [0078], Line 10 recites “input waveform 1013” should be “input waveform 1304”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yoscovich et. al. (U.S. Publication No 2015/0280608 A1).
Regarding claims 1 and 11, Yoscovich et. al. teaches an apparatus and method comprising (Fig. 1A): a first power interface (e.g. DC 350V)(Fig. 1A);
a second power interface (e.g. AC out)(Fig. 1A);
a multi-stage switching system (e.g. S1A-S6A, S1B-S6B, S1C-S6C, S1D-S6D)(Fig. 1A), coupled to the first power interface and to the second power interface, the multi-stage switching system comprising a plurality of switching stages (e.g. S1A-S6A, S1B-S6B, S1C-S6C, S1D-S6D)(Fig. 1A) to convert between Direct Current (DC) power at the first power interface and Alternating Current (AC) power at the second power interface, the switching stages being coupled together in a circuit path across the second power interface (Implied Fig. 1A);
a controller (e.g. 10)(Fig. 3)(Para [0062], “each of the switches may be controlled by an output from a processor 10”), coupled to the multi-stage switching system, to control switching in one of the switching stages at high frequency relative to a frequency of the AC power (Para [0090], “FIG. 4, the output of the high frequency stage is a rectified sine-wave”), and to control switching of another one of the switching stages at lower frequency relative to the frequency of the AC power (Para [0090], “he low frequency stage inverts the rectified sine-wave to positive and negative, to create a true sine-wave. The low-frequency stage may be configured to invert the signal whenever it is needed. In this embodiment, the low frequency stage has a number of switches such as four switches S10, S11, S12, S13”).
Regarding claim 2 and 12, Yoscovich et. al. teaches a filter stage, coupled to the second power interface, to filter the AC power at the second power interface (e.g. L1/L2)(Fig. 1A).
Regarding claim 3 and 13, Yoscovich et. al. teaches wherein each switching stage comprises a polarity switching stage to control polarity of the AC power at the second power interface (Para [0134], “In the phase blocks P3 of FIGS. 30-32, switches (e.g., MOSFET transistors) T77A, T81A, T81B, T83A, T77C, T81E, T81F, T83C, T83D, T78A, T82A, T82B, T84A, and T78C, T78C, T82E, T82F, T84C, T84D may be fast switching while the remaining switches are switched slowly according to the polarity of a 50 Hz sine wave”).
Regarding claim 4 and 14, Yoscovich et. al. teaches a polarity switching stage, coupled to the second power interface, to control polarity of the AC power at the second power interface (Para [0120], “The input capacitor Cin of each phase block can provide the half voltage since the switches to Vh and Vl may slowly switch according to the polarity of the 50 Hz sine-wave of each phase. Each phase may transition polarity at a different time”).
Regarding claim 5 and 15, Yoscovich et. al. teaches wherein the lower frequency is twice the frequency of the AC power (Para [0092], “in order to compensate for the low frequency pulsation, such as a low frequency pulse of around 100 Hz”)(Para [0061], “The duty cycle of the control signals may be varied according to required conversion ratio of the inverter, which may include a full range of duty cycles starting from 0 and ending up at 1 throughout, for example, a 50/60 Hz sine wave).
Regarding claim 6 and 16, Yoscovich et. al. teaches wherein the switching stages are identical in structure (Para [0057], “The switches may be coupled to a number of capacitors and/or inductors which may be utilized to smooth a sine-wave of an AC output of the inverter. For example, a plurality of switch banks S1A-S6A, S6B-S1B, S1C-S6C, and/or S6D-S1D may be disposed in any suitable configuration such as that shown in FIG. 1A. Each of the banks of MOSFET transistors may be variously configured to include two, three, four, five, six, seven, eight, nine, ten, eleven, twelve or more transistors”)(see Fig. 1A).
Regarding claim 7 and 17, Yoscovich et. al. teaches wherein the controller is configured to operate the switching stages to provide respective output voltages in sequential order in which the switching stages are coupled in the circuit path across the second power interface (Para [0062], “Referring to FIG. 3, each of the switches may be controlled by an output from a processor 10”)(Para [0079], “the control illustrated in FIG. 2A allows the switches S1A-S6A, S6B-S1B, S1C-S6C, and S6D-S1D to be switched all within one period, in this embodiment with the switching of switches in one bank to be offset as shown in FIG. 2A”)
Regarding claim 8 and 18, Yoscovich et. al. teaches wherein the controller is configured to operate the switching stages to provide respective output voltages out of sequential order in which the switching stages are coupled in the circuit path across the second power interface (Para [0090], “The low-frequency stage may be configured to invert the signal whenever it is needed. In this embodiment, the low frequency stage has a number of switches such as four switches S10, S11, S12, S13. In this example, the positive cycle of the sine-wave can be achieved by having the top-left S10 and bottom right S11, switching to on”)(See Fig. 4).
Regarding claim 9 and 19, Yoscovich et. al. teaches wherein an order in which the controller is configured to operate the switching stages to provide respective output voltages varies between half cycles of the AC power (Para [0105], “The circuit shown in FIG. 10 maintains seven levels since, in each 50 Hz half cycle, the circuit shown in FIG. 10 provides three different levels resulting in six levels in addition to the zero level”), such that any individual switching stage is on and provides an output voltage for different periods of time in a sequence of half cycles and is to be switched at the high frequency in one of those half cycles in the sequence (Para [0104], “for example, 50 Hz complementarily while the other 6 switches S4K-S6K, S4L-S6L connected to capacitors C38-40 act as fast switches (e.g., high frequency switches) using a flying capacitor control method as described herein where the control signals to the switches S4L-S6L are inverted versions of the control signals to the switches S4K-S6K”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable Yoscovich et. al. (U.S. Publication No 2015/0280608 A1) in view of Baeurle (U.S. Publication No 2021/0091701 A1).
Regarding claim 21, Yoscovich et. al. teaches an apparatus comprising (Fig. 1A): a first power interface (e.g. DC 350V)(Fig. 1A);
a second power interface (e.g. AC out)(Fig. 1A);
a multi-stage switching system (e.g. S1A-S6A, S1B-S6B, S1C-S6C, S1D-S6D)(Fig. 1A), coupled to the first power interface and to the second power interface, the multi-stage switching system comprising a plurality of switching stages (e.g. S1A-S6A, S1B-S6B, S1C-S6C, S1D-S6D)(Fig. 1A) to convert between Direct Current (DC) power at the first power interface and Alternating Current (AC) power at the second power interface, the switching stages being coupled together in a circuit path across the second power interface (Implied Fig. 1A);
a controller (e.g. 10)(Fig. 3)(Para [0062], “each of the switches may be controlled by an output from a processor 10”), coupled to the multi-stage switching system
Yoscovich et. al. does not teach control switching in the switching stages based on a digital word that comprises m bits, wherein the controller is configured to generate a pulse width modulation (PWM) output based on n least significant bits of the digital word to control switching in one of the switching stages, and to generate further outputs based on (m-n) most significant bits of the digital word to control switching in switching stages other than the one of the switching stages.
However, Baeurle discloses control switching in the switching stages based on a digital word that comprises m bits (Para [0071], “In one example, the command signal 118 could be representative of an N-bit digital word. Further, the system controller 102 could apply coding to the command signal 118”), wherein the controller is configured to generate a pulse width modulation (PWM) output (Para [0070], “The system controller 102 determines whether the switch controllers 114, 615 should turn on or turn off the power switches 679, 680 based on system inputs 699. Example system inputs 699 include pulse width modulated (PWM) signal for a general purpose motor drive, a turn-on and turn-off sequence of a multi-level power converter, or a system fault turn-off request”) based on n least significant bits of the digital word to control switching in one of the switching stages, and to generate further outputs based on (m-n) most significant bits of the digital word to control switching in switching stages other than the one of the switching stages (Para [0057], “The system controller 102 is configured to output a command signal to one or more half-bridge modules 566, 567, and 568””… In one example, the command signal 118 could be representative of a digital word. Further, the system controller 102 could apply coding to the command signal 118. As will be further illustrated with respect to FIG. 5B, the system controller 102 outputs a command signal 118 to at least one switch controller of one or more half-bridge modules 566, 567, and 568 via the communication bus 577”).
Therefore, it would be obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to configure the “apparatus” teachings of Yoscovich et. al. such that it comprises “control switching in the switching stages based on a digital word that comprises m bits, wherein the controller is configured to generate a pulse width modulation (PWM) output based on n least significant bits of the digital word to control switching in one of the switching stages, and to generate further outputs based on (m-n) most significant bits of the digital word to control switching in switching stages other than the one of the switching stages” as taught by Baeurle. The reason for doing so would be to provide accuracy, flexibility, and ability to handle complex control algorithms.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONATHAN W SOILEAU whose telephone number is (571)272-6650. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CT.
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/JONATHAN WALTER SOILEAU/Examiner, Art Unit 2838
/CRYSTAL L HAMMOND/Supervisory Primary Examiner, Art Unit 2838