Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-26 and 30-35 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18, it refers to “the weight reflecting the change in the transmission time;” however, that term has not been defined (lacks antecedent basis). Claim 17 defines “a weight corresponding to the transmission time,” but there is not definition a weight reflecting a change in the transmission time. Claims 19-26 depend on claim 18; therefore, they are indefinite for the same reason. Further, claim 30 recites commensurate subject matter as claim 18; therefore, it is indefinite for the same reason. Claim 31 depends on claim 30; therefore it is indefinite for the same reason.
Claims 32 and 35 recites the limitation “the micro controller.” Further, claim 32 refers to “the amount” and “the weight,” which are defined in claims 29 and 30; however, claim 32 depends on claim 27. There is insufficient antecedent basis for this limitation in the claim. Claims 33 and 34 depend on claim 32; therefore, they are indefinite for the same reason.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-22, 25-33, and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bloks (US 2004/0117577) and further in view of Chang (US 2008/0307130).
Regarding claim 16, Bloks teaches: A memory control system comprising:
master processors (¶ 21, “Multiple processors may be used in the computing device 100 for processing information in conjunction with processor 202”) each configured to transmit a command and deadline information for the command (¶ 30, “FIG. 3 illustrates several parameters of a real-time service request by a real-time requester . . . issues the request at current time T for service to the scheduler 205 and the required service completion time”); and
a slave processor configured to receive commands (¶ 55, “a real-time request control circuit 310 receives real-time requests from clients in a computing device”), set a schedule according to the deadline information (¶ 36, “the scheduler 205 updates the schedule of all pending and potential requests once each clock cycle of the shared resource”), select a command in order of earliest deadline according to the schedule (¶ 34, “The process closest to its deadline has highest priority”), and perform a process for the selected command (¶ 55, “grants shared-resource access to these requesters”),
wherein the slave processor is configured to reconfigure the schedule in response to a change in the deadline information (¶ 50, “This is a dynamic ordering system, and the order of requests will likely change each time the algorithm is run” and ¶ 57, “The reorder logic circuit 330 performs the task of arranging the M pairs of (Ti, Di) for each request R in ascending order of Ti value”).
Bloks does not teach; however, Chang discloses: each of the master processors is configured to provide the deadline information in which a deadline for the command is changed in response to a change in a transmission time for which the command is transmitted to the slave processor (¶ 28, “During each scan, logic module 220 may recalculate the deadline value of each pending request and determine a new deadline value as follows: New deadline=original deadline-(Timestamp_Current-Timestamp_Origin)”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of each of the master processors is configured to provide the deadline information in which a deadline for the command is changed in response to a change in a transmission time for which the command is transmitted to the slave processor, as taught by Chang, in the same way to the master processors, as taught by Bloks. Both inventions are in the field of deadline based scheduling, and combining them would have predictably resulted in “address[ing] problems associated with isochronous I/O requests encountered with media streaming applications through deadline management,” as indicated by Chang (¶ 25).
Regarding claim 17, Chang teaches: The memory control system of claim 16, wherein each of the master processors is configured to generate priority information for the command when the command is generated (¶ 27, “Each request may carry information to characterize it as a normal, a high priority, or an isochronous reques”), and generate the deadline information by combining a weight corresponding to the transmission time on a current basis with the priority information (¶ 30, “The term "Ttx*NumberOfOutstandingHighPriorityRequests" may be necessary to give the device enough time padding to finish servicing high priority requests first while meeting the deadline of the subsequently issued isochronous requests” and ¶ 31, “MINTV=(Tseek+Trotational_delay(RPM dependent)+Ttx+Ttx*NumberOfOutstandingHighPriorityRequests)”).
Regarding claim 18, Chang teaches: The memory control system of claim 17, wherein each of the master processors is configured to generate an amount of change in the transmission time after transmitting the command and the deadline information (¶ 28, “During each scan, logic module 220 may recalculate the deadline value of each pending request and determine a new deadline value as follows: New deadline=original deadline-(Timestamp_Current-Timestamp_Origin)”), change the deadline information by combining the weight reflecting the change in the transmission time with the priority information (¶ 30, “MINTV=(Expected time for the isochronous request to complete)+(Estimated total time of all other outstanding commands currently in the native queue of the device to complete)+(Estimated time padding for the isochronous request to propagate back to higher stack requestor upon completion)”), and provide the changed deadline information to the slave processor (¶ 29, “logic module 220 may issue the request to the data storage device”).
Regarding claim 19, Chang teaches: The memory control system of claim 18, wherein each of the master processors is configured to periodically generate the amount of change in the transmission time (¶ 28, “During each scan, logic module 220 may recalculate the deadline value of each pending request and determine a new deadline”), periodically change the deadline information (¶ 37, “the dispatch policy algorithm may calculate new deadlines for any isochronous requests in the isochronous queue (elements 325 and 320)”), and periodically provide the changed deadline information to the slave processor (¶ 28, “logic module 220 may only update the "New deadline" value of the request packet at the time of issuance to the data storage device, or transfer to issuance module 270”).
Regarding claim 20, Bloks teaches: The memory control system of claim 19, wherein the slave processor is configured to periodically reconfigure the schedule in response to receipt of the changed deadline information (¶ 36, “the scheduler 205 updates the schedule of all pending and potential requests once each clock cycle of the shared resource” and ¶ 57, “The reorder logic circuit 330 performs the task of arranging the M pairs of (Ti, Di) for each request R in ascending order of Ti value”).
Regarding claim 21, Bloks and Chang teach: The memory control system of claim 19, wherein each of the master processors includes: a command generator configured to generate the command and the priority information for the command (Chang, ¶ 39, “processor 105 may generate an isochronous read request to retrieve data from CD ROM drive 170” and ¶ 27, “Each request may carry information to characterize it as a normal, a high priority, or an isochronous request”); a buffer configured to buffer the command and transmit the command to the slave processor (Bloks, ¶ 27, “Input devices of this nature must offload their data quickly into main memory 221 before more data arrives which would overflow their small internal buffers”); and a deadline provider configured to generate the amount of change in the transmission time with state information of the buffer referring to a synchronization signal for driving the buffer (Chang, ¶ 28, “New deadline=original deadline-(Timestamp_Current-Timestamp_Origin);” and ¶ 30, “Ttx may represent the average time to transmit requested data blocks to or from the data storage device”), receive the priority information (¶ 27, “Each request may carry information to characterize it as a normal, a high priority, or an isochronous reques”), and output the deadline information generated by combining the weight reflecting the amount of change in the transmission time with the priority information (Chang, ¶ 30, “the minimum threshold value (MINTV) may be calculated with the following criterion: MINTV=(Storage device interface overhead latency for data access+Ttx+Ttx*NumberOfOutstandingHighPriorityRequests)”).
Regarding claim 22, Bloks teaches: The memory control system of claim 21, wherein the command generator is configured to generate the command when data is read from a memory or data is written to the memory (¶ 1, “one or more processors read data from this memory, perform one or more processing steps, and write a result back into memory”).
Regarding claim 25, Bloks and Chang teach: The memory control system of claim 21, wherein the deadline provider is configured to receive a clock signal with a shorter period than the synchronization signal (Bloks, ¶ 29, “the scheduler 205 updates the actual/potential request queue every clock cycle”), periodically generate the amount of change in the transmission time using the clock signal (Chang, ¶ 28, “New deadline=original deadline-(Timestamp_Current-Timestamp_Origin);”), periodically change the deadline information (Chang, ¶ 28, “logic module 220 may recalculate the deadline value of each pending request”), and periodically provide the deadline information to the slave processor (Bloks, ¶ 36, “the scheduler 205 updates the schedule of all pending and potential requests once each clock cycle of the shared resource”).
Regarding claim 26, Bloks teaches: The memory control system of claim 21, wherein the slave processor includes: a buffer circuit configured to stack the commands of the master processors (claim 4, “a timer circuit having registers operable to hold a plurality of M real-time requests”); an arbiter configured to receive the deadline information, set the schedule with the deadline information, and provide a selection signal for selecting the command in order of earliest deadline according to the schedule (¶ 57, “The reorder logic circuit 330 performs the task of arranging the M pairs of (Ti, Di) for each request R in ascending order of Ti value”); and a selector configured to select and output the command corresponding to the selection signal among the commands stacked in the buffer circuit (¶ 58, “The MIN value select circuit 350 finds the earliest (or (MINi(T.sub.L1)) of all these values (T.sub.s) and passes it to its output”).
Claims 27-33 and 35 recite commensurate subject matter as claims 16-18, 21, 22, 25, and 26. Therefore, they are rejected for the same reasons.
Claim(s) 23 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bloks and Chang, as applied above, and further in view of Mallet (US 2010/0328329).
Regarding claim 23, Bloks and Chang do not teach; however, Mallet discloses: the buffer is configured to buffer data in units of horizontal lines (¶ 74, “there are four line buffers 306, which each stores a full line of pixels from the input video signal” and ¶ 87, “FIG. 6 shows the conventional way of dividing up the array into four horizontal lines {a.sub.00, a.sub.01, a.sub.02, a.sub.03}, {a.sub.10, a.sub.11, a.sub.12, a.sub.13}, {a.sub.20, a.sub.21, a.sub.22, a.sub.23}) {a.sub.30, a.sub.31, a.sub.32, a.sub.33}, each horizontal line containing four pixels”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the buffer is configured to buffer data in units of horizontal lines, as taught by Mallet, in the same way to the buffer, as taught by Bloks and Chang. Both inventions are in the field of deadline-based scheduling, and combining them would have predictably resulted in “facilitating (simultaneous) access to pixels in adjacent rows or columns,” as indicated by Mallet (abstract).
Claim 34 recites commensurate subject matter as claim 23. Therefore, it is rejected for the same reason.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bloks and Chang, as applied above, and further in view of MacInnis (US 2012/0268655).
Regarding claim 24, Bloks and Chang do not teach; however, MacInnis discloses: the buffer is configured to use a horizontal synchronization signal as a synchronization signal for buffering the command (¶ 189, “The system in step 528 preferably detects a horizontal sync (HSYNC) which signifies a new display line” and ¶ 188, “The system in step 526 preferably stores composited graphics data in the line buffers”).
It would have been obvious to a person having ordinary skill in the art, at the effective filing date of the invention, to have applied the known technique of the buffer is configured to use a horizontal synchronization signal as a synchronization signal for buffering the command, as taught by MacInnis, in the same way to the buffer, as taught by Bloks and Chang. Both inventions are in the field of display and memory interface systems, and combining them would have predictably resulted in “synchroniz[ing] the graphics line buffers to the memory clock and the display clock,” as indicated by MacInnis (¶ 183).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB D DASCOMB whose telephone number is (571)272-9993. The examiner can normally be reached M-F 9:00-5:00.
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/JACOB D DASCOMB/Primary Examiner, Art Unit 2198
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