DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 17 recites the limitation "the fifth FET" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the second polysilicon pattern" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 13-14 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. The limitation such as “An operation chip” of claim 13 does not further define the integrated circuit of the independent Claim 1; and “A computing apparatus” of Claim 14 does not further define the integrated circuit of the independent Claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2 and 8-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by GOETZ HOWARD (CN 115053284A; hereinafter referred to as Goetz).
With regard to claim 1, Goetz discloses in Figure 6a, 6b and 7 an integrated circuit comprising multiple dynamic registers arranged in a row in a spatial layout, each of which has its own input data signal and output data signal (D, Q), and receives the same control signal (LD, LDB). The dynamic latches include a first dynamic latch arranged in the first row and a second dynamic latch arranged in the second row adjacent to the first row. The first dynamic latch includes a first tri-state gate (the gate of the PMOSFET in the upper part of Figure 7 is connected to LD in Figure 6a, or the gate of the NMOSFET in the upper part of Figure 7 is connected to LDB in Figure 6a), and the second dynamic latch includes a second tri-state gate (the gate of the PMOSFET in the lower part of Figure 7 is connected to LD in Figure 6a, or the gate of the NMOSFET in the lower part of Figure 7 is connected to LDB in Figure 6a). The first tri-state gate includes a first field-effect transistor (FET), and the second tri-state gate includes a second FET of the same polarity as the first FET. In the spatial layout, the first FET and the second FET are adjacent to each other, and the first FET and the second FET use a first polysilicon pattern (LD, LDB) continuously extending across the first boundary between the first row and the second row as the gate terminal to receive the same first control signal (as depicted in Fig. 6b below).
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With regard to claim 2, the recitation, “wherein the first FET and the second FET are P-type field effect transistors or N-type field effect transistors”, is also anticipated by Goetz, which is based on the recitation “The first tri-state gate includes a first field-effect transistor (FET), and the second tri-state gate includes a second FET of the same polarity as the first FET”, as recited in the independent Claim 1.
With regard to claim 8, wherein the first tristate gate and the second tristate gate have a same logic circuit diagram. Note that they share the common buses LD and LDB (as depicted in Figures 6a and 6b).
With regard to claim 9, the recitation, “where in the first FET and the second FET share a same substrate region continuously extending across the first boundary”, is also inherently anticipated by Goetz, which is based on the recitation “In the spatial layout, the first FET and the second FET are adjacent to each other, and the first FET and the second FET use a first polysilicon pattern (LD, LDB) continuously extending across the first boundary between the first row and the second row as the gate terminal to receive the same first control signal”, as recited in the independent Claim 1.
With regard to claim 10, wherein the first dynamic register and the second dynamic register share one of a power supply rail or a ground rail, and the one of the power supply rail (VDD) or the ground rail (VSS) is arranged at the first boundary (as depicted in Fig. 6b).
With regard to claim 11, wherein the first dynamic register and the second dynamic register comprise a dynamic latch (see paragraphs [n0042] - [n0043]).
With regard to claim 12, wherein the first tristate gate and the second tristate gate are implemented using complementary metal oxide semiconductor field effect transistors (as depicted in Fig. 6a).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13, 14, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goetz.
With regard to claim 13, the recitation, “An operation chip, comprising at least one integrated circuit according to claim 1.” merely specifies the intended use or environment in which the claimed integrated circuit is employed. The prior art discloses the structural limitations of the integrated circuit recited in the independent Claim 1. The recitation of an “operation chip” does not require any additional structural limitation or otherwise distinguish the claimed integrated circuit from the prior-art integrated circuit. It is well established that a recitation directed to the intended use or manner of use of a claimed apparatus does not distinguish the claimed apparatus from a prior-art apparatus that otherwise satisfies the claimed structural limitations. See Ex parte Masham, 2 USPQ2d 1647 (BPAI 1987). Accordingly, the recitation of an “operation chip” does not render the claimed apparatus patentably distinct from the prior art. Therefore, the recited intended use does not overcome the rejection under 35 U.S.C. § 103.
With regard to claim 14, the recitation, “A computing apparatus, comprising: at least one operation chip according to claim 13; a control chip; a power supply module; and a radiator, wherein the control chip is coupled to the at least one operation chip and is configured for controlling operation of the at least one operation chip; wherein the power supply module is configured for providing power to the at least one operation chip and/or the control chip; and wherein the radiator is configured for dissipating heat for the at least one operation chip, the control chip, and/or the power supply module,” recites a combination of known components and their respective functional relationships. To the extent the recitation of a “computing apparatus” or the specified manner of use of the components is relied upon to distinguish the claimed apparatus, such recitation does not impart patentable weight where the prior art otherwise discloses the claimed structural arrangement and associated functional relationships. The prior art discloses an operation chip according to claim 13, a control chip coupled to the operation chip for controlling operation thereof, a power supply module configured to provide power to the operation chip and/or the control chip, and a radiator configured to dissipate heat from the components. It is well established that a recitation directed merely to the intended use or manner of use of a claimed apparatus does not distinguish the claimed apparatus from a prior-art apparatus that otherwise satisfies the claimed structural limitations. See Ex parte Masham, 2 USPQ2d 1647 (BPAI 1987). Accordingly, to the extent the recitation of a “computing apparatus” constitutes an intended use, such recitation does not render the claimed apparatus patentably distinct from the prior art. Therefore, the recited intended use does not overcome the rejection under 35 U.S.C. § 103.
With regard to claim 17, the recitation, “The integrated circuit according to claim 9, wherein source terminals of the first FET and the fifth FET are coupled together.” (emphasis added) is also rendered obvious over Goetz. Goetz discloses an integrated circuit having first and fifth FETs. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Goetz such that the source terminals of the first FET and the fifth FET are coupled together. Such a modification would have involved the use of a known circuit configuration to achieve the predictable result of providing the claimed structural relationship between the first FET and the fifth FET. Accordingly, the claimed limitation would have been an obvious design choice for one of ordinary skill in the art, and claim 17 is therefore unpatentable under 35 U.S.C. § 103 over Goetz.
With regard to claim 19, the recitation, “wherein the first polysilicon pattern and the second polysilicon pattern are aligned in a column direction” is also rendered obvious over Goetz. Goetz discloses an integrated circuit having first and second polysilicon patterns. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the integrated circuit of Goetz such that the first and second polysilicon patterns are aligned in a column direction. Such a modification would have involved the use of a known circuit configuration to achieve the predictable result of providing the claimed structural relationship between the first FET and the fifth FET. Accordingly, the claimed limitation would have been an obvious design choice for one of ordinary skill in the art, and claim 19 is therefore unpatentable under 35 U.S.C. § 103 over Goetz.
Reference of Note
The prior art of Record and not relied upon is considered pertinent to applicant’s disclosure:
Zhang al. (US 11,979,150) teaches a clock-controlled register designed to hold digital data more reliably. The register includes an input, an output, a clock input, a switching stage, a latch stage, an output driver, and a leakage compensation path.
Allowable Subject Matter
Claims 3-7, 15, 16, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/HAI L NGUYEN/Primary Examiner, Art Unit 2836 August 14, 2026
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