Prosecution Insights
Last updated: April 19, 2026
Application No. 18/724,467

SOLID ELECTROLYTIC CAPACITOR

Non-Final OA §103
Filed
Jun 26, 2024
Examiner
SINCLAIR, DAVID M
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Panasonic Intellectual Property Management Co., Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
87%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allow Rate
833 granted / 1232 resolved
At TC average
Strong +20% interview lift
Without
With
+19.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
42 currently pending
Career history
1274
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1232 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Email Communication Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Freeman et al. (US 2010/0265634) in view of Kurita et al. (US 2012/0087062). In regards to claim 1, Freeman ‘634 discloses a solid electrolytic capacitor comprising: a capacitor element (fig. 6; [0033]); and an exterior body (6 – fig. 6; [0033]) that seals the capacitor element, wherein the capacitor element includes an anode body (2 – fig. 6; [0033]), a dielectric layer (3 – fig. 6; [0033]) that is formed on a surface of the anode body, a cathode part (5 – fig. 6; [0033]) that covers at least a portion of the dielectric layer, an anode lead (7 – fig. 6; [0033]) with one end portion electrically connected to the anode body, and a cathode lead (8 – fig. 6; [0033]) with one end portion electrically connected to the cathode part, another end portion of the anode lead and another end portion of the cathode lead are drawn out from the exterior body (seen in fig. 6), the cathode part includes a solid electrolyte layer ([0033]) that covers at least a portion of the dielectric layer. Freeman ‘634 fails to explicitly disclose a total amount of gas generated in the following (e) and the following (f) is 1600 µL or less, when the solid electrolytic capacitor is subjected to: (a) heating at 155°C for 24 hours; (b) cooling to 30°C at 60% RH or less; (c) leaving to stand for 168 hours at 30°C and 60% RH; (d) cutting at a center in a length direction at 25°C and under an inert atmosphere; (e) heating the cut solid electrolytic capacitor to 150°C at a rate of 50°C/min under an inert atmosphere, heating from 150°C to 200°C at a rate of 16.7°C/min, heating from 200°C to 260°C at a rate of 40°C/min, continuously heating at 260°C for 10 seconds, and cooling from 260°C to 30°C at a rate of 16.7°C/min; and (f) repeating the (e) two more times. Kurita ‘062 discloses that the total amount of gas generated during reflow is a result effective variable, particularly for reducing swelling of the outer package which allows for improved reliability of the capacitor ([0052] & [0055]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Freeman ‘634 such that a total amount of gas generated in the following (e) and the following (f) is 1600 µL or less, when the solid electrolytic capacitor is subjected to: (a) heating at 155°C for 24 hours; (b) cooling to 30°C at 60% RH or less; (c) leaving to stand for 168 hours at 30°C and 60% RH; (d) cutting at a center in a length direction at 25°C and under an inert atmosphere; (e) heating the cut solid electrolytic capacitor to 150°C at a rate of 50°C/min under an inert atmosphere, heating from 150°C to 200°C at a rate of 16.7°C/min, heating from 200°C to 260°C at a rate of 40°C/min, continuously heating at 260°C for 10 seconds, and cooling from 260°C to 30°C at a rate of 16.7°C/min; and (f) repeating the (e) two more times to obtain a capacitor with improved reliability as outer packaging swelling is reduced, as taught by Kurita ‘062. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In regards to claim 2, Freeman ‘634 as modified by Kurita ‘062 further discloses wherein the solid electrolyte layer contains a conjugated polymer and a dopant, and the dopant includes a benzenesulfonic acid compound ([0040-0045] of Freeman ‘634). In regards to claim 3, Freeman ‘634 as modified by Kurita ‘062 further discloses, wherein the solid electrolyte layer contains a conjugated polymer and a dopant, and the dopant includes a compound that has an aromatic ring, at least one sulfo group bonded to the aromatic ring, and at least two functional groups selected from the group consisting of a carboxy group bonded to the aromatic ring and a hydroxy group bonded to the aromatic ring ([0040-0045] of Freeman ‘634) In regards to claim 4, Freeman ‘634 as modified by Kurita ‘062 further discloses wherein the solid electrolyte layer contains a conjugated polymer and a dopant, and the dopant includes a compound that has an aromatic ring, at least one sulfo group bonded to the aromatic ring, and at least two carboxy groups bonded to the aromatic ring, and does not have a hydroxy group ([0040-0045] of Freeman ‘634) In regards to claim 5, Freeman ‘634 as modified by Kurita ‘062 further discloses wherein the aromatic ring is a benzene ring ([0045] of Freeman ‘634) Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 6,229,687) in view of Kurita ‘062. In regards to claim 1, Wada ‘687 discloses a solid electrolytic capacitor comprising: a capacitor element (11 – fig. 2; C2:L41-62); and an exterior body (17 – fig. 7; C4:L47) that seals the capacitor element, wherein the capacitor element includes an anode body (5 – fig. 2; C2:L41-62), a dielectric layer (7 – fig. 2; C2:L41-62) that is formed on a surface of the anode body, a cathode part (8-10 – fig. 2; C2:L41-62) that covers at least a portion of the dielectric layer, an anode lead (12 – fig. 4-5; C2:L63) with one end portion electrically connected to the anode body, and a cathode lead (12 – fig. 4-5; C2:L63) with one end portion electrically connected to the cathode part, another end portion of the anode lead and another end portion of the cathode lead are drawn out from the exterior body (seen in fig. 7), the cathode part includes a solid electrolyte layer (8 – fig. 2; C2:L41-62) that covers at least a portion of the dielectric layer. Wada ‘687 fails to explicitly disclose a total amount of gas generated in the following (e) and the following (f) is 1600 µL or less, when the solid electrolytic capacitor is subjected to: (a) heating at 155°C for 24 hours; (b) cooling to 30°C at 60% RH or less; (c) leaving to stand for 168 hours at 30°C and 60% RH; (d) cutting at a center in a length direction at 25°C and under an inert atmosphere; (e) heating the cut solid electrolytic capacitor to 150°C at a rate of 50°C/min under an inert atmosphere, heating from 150°C to 200°C at a rate of 16.7°C/min, heating from 200°C to 260°C at a rate of 40°C/min, continuously heating at 260°C for 10 seconds, and cooling from 260°C to 30°C at a rate of 16.7°C/min; and (f) repeating the (e) two more times. Kurita ‘062 discloses that the total amount of gas generated during reflow is a result effective variable, particularly for reducing swelling of the outer package which allows for improved reliability of the capacitor ([0052] & [0055]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wada ‘687 such that a total amount of gas generated in the following (e) and the following (f) is 1600 µL or less, when the solid electrolytic capacitor is subjected to: (a) heating at 155°C for 24 hours; (b) cooling to 30°C at 60% RH or less; (c) leaving to stand for 168 hours at 30°C and 60% RH; (d) cutting at a center in a length direction at 25°C and under an inert atmosphere; (e) heating the cut solid electrolytic capacitor to 150°C at a rate of 50°C/min under an inert atmosphere, heating from 150°C to 200°C at a rate of 16.7°C/min, heating from 200°C to 260°C at a rate of 40°C/min, continuously heating at 260°C for 10 seconds, and cooling from 260°C to 30°C at a rate of 16.7°C/min; and (f) repeating the (e) two more times to obtain a capacitor with improved reliability as outer packaging swelling is reduced, as taught by Kurita ‘062. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada ‘687 as modified by Kurita ‘062 as applied to claim 1 above, and further in view of JP2019207905A hereafter referred to as Nakatsugawa. In regards to claim 6, Wada ‘687 as modified by Kurita ‘062 further discloses wherein each of the anode lead and the cathode lead is divided into an embedded part that includes the one end portion and is embedded in the exterior body and an exposed part that includes the other end portion and is exposed from the exterior body (fig. 7 of Wada ‘687), at least one of the anode lead and the cathode lead has a rough surface with an interface developed area ratio Sdr (C4:L25-41 of Wada ‘687 – surface is roughened and thus will inherently have an Sdr), and the rough surface is present on at least a portion of the embedded part (C4:L25-41 of Wada ‘687– entire lead frame is sandblasted prior to resin packaging being formed). Wada ‘687 as modified by Kurita ‘062 fails to disclose the Sdr is 0.4 or more. Nakatsugawa discloses a lead frame has a rough surface with an interface developed area ratio Sdr of 0.4 or more (abstract). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Wada ‘687 as modified by Kurita ‘062 such that the Sdr is 0.4 or more as taught by Nakatsugawa to ensure excellent adhesion between the lead frame and exterior resin. In regards to claim 7, Wada ‘687 as modified by Kurita ‘062 and Nakatsugawa further discloses wherein each of the anode lead and the cathode lead has the rough surface (C4:L25-41 of Wada ‘687), and each of the rough surface is present on at least a portion of the embedded part (C4:L25-41 of Wada ‘687 – entire lead frame is sandblasted). In regards to claim 8, Wada ‘687 as modified by Kurita ‘062 and Nakatsugawa further discloses wherein the embedded part of the anode lead has a contact surface p that is in contact with the exterior body (fig. 4 of Wada ‘687), the embedded part of the cathode lead has a contact surface n that is in contact with the exterior body (fig. 4 of Wada ‘687), a percentage of the area of the rough surface in the area of the contact surface p is 50% or more (C4:L25-41 of Wada ‘687 – entire lead frame is sandblasted), and a percentage of the area of the rough surface in the area of the contact surface n is 50% or more (C4:L25-41 of Wada ‘687 – entire lead frame is sandblasted). In regards to claim 9, Wada ‘687 as modified by Kurita ‘062 and Nakatsugawa further discloses wherein the rough surface is present on at least a portion of the embedded part and is present on at least a portion of the exposed part (C4:L25-41 of Wada ‘687 – entire lead frame is sandblasted). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2009/0195966 – [0022-0026] US 2013/0236636 – [0037-0042] US 2016/0118197 – [0031] Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David M Sinclair/Primary Examiner, Art Unit 2848
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Prosecution Timeline

Jun 26, 2024
Application Filed
Jan 07, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
87%
With Interview (+19.6%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1232 resolved cases by this examiner. Grant probability derived from career allow rate.

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