CTNF 18/724,611 CTNF 92511 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Status of the Application 2. Claim 1-2, 7, and 9 have been examined in this application. Claim 3-6, and 8 have been canceled. This communication is the first action on the merits. Drawings 3. The drawings filed on 6/27/24 are acceptable for examination proceedings. Claim Rejections - 35 USC § 112 07-30-02 AIA 4. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 5. Claim 1 recites the limitation "wherein the first central processing unit includes an outputter to output, to the second central processing unit, an operation determination signal for determining that the first central processing unit is in operation when a voltage drop in an internal power supply in the first central processing unit is not detected , and the processing circuitry selects to stop or not to stop an operation of the second central processing unit when the second central processing unit does not acquire the operation determination signal , and stops the operation of the second central processing unit when the processing circuitry selects to stop the operation of the second central processing unit, and does not stop the operation of the second central processing unit when the processing circuitry selects not to stop the operation of the second central processing unit" renders the claim indefinite because it is unclear and does not read appropriate. The output of “an operation determination signal” is does not clearly define i.e., how the signal is determined means based on what? and how it is implemented to make selection of stop or not to stop of second CPU. Also claim 1, 7, and 9 recite the limitation of “ selects to stop or not to stop an operation of the second central processing unit when the second central processing unit does not acquire the operation determination signal .” The way the claim limitation is claimed the selection is made without need of operation determination signal, and hence operation determination signal is not required at all. Therefore the claimed limitation is not clear and definite. Examiner’s Note : Refer to the current case PG Pub: 2025/0060734, Para. [0014] for clarified language of the current invention includes how the selection is made and how the CPUs are operated between stop mode and fallback mode. Also refer to Para. [0069]-[0070] that PLC can perform selection in the first CPU 310 with an abnormality to select between a stop mode in which all the CPUs 310 , 320 , 330 , and 340 stop operating to stop the operation of the entire control system and a fallback mode in which the CPUs 320 , 330 , and 340 with no abnormality continue operating without suspending the operation of the entire control system. This allows the PLC 1 according to the present embodiment to select to stop or to continue the operation of the entire control system when an abnormality occurs. 6. Claim 2 is depend on claim 1 and hence rejected under 35 U.S.C 112(b) rejection. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA 8. Claim s 1-2, 7, and 9 are rejected under 35 U.S.C. 102( a) (1 ) as being anticipated by Spears (US Patent: 6304981) . 9. Regarding claim 1 , Spears discloses: A programmable logic controller including a first central processing unit and a second central processing unit capable of controlling a control target device independently of each other, the programmable logic controller comprising: processing circuitry (e.g., Turning now to FIG. 6, a block diagram depicting a typical hardware management system is shown. The hardware management system 300 may, for example, monitor the operation of an information handling system (see FIGS. 1 through 4) for events or conditions requiring the system to be shut down or reset and may be utilized to implement the adaptive shutdown system and method of the present invention. The A information handling system (see FIGS. 1 through 5) may include a multiprocessor system 310 having two or more processors 312, 314 & 316 ) (Col. 5, Ln. 64-67, Fig. 6-7); and a transmitter-receiver (e.g., For example, the input/output system 216 may comprise a serial port, parallel port, infrared port, network adapter, printer adapter, radio-frequency (RF) communications adapter, universal asynchronous receiver-transmitter (UART) port, etc., for interfacing between corresponding I/O devices such as a mouse, joystick, trackball, trackpad, trackstick, infrared transducers, printer, modem, RF modem, bar code reader, charge-coupled device (CCD) reader, scanner, compact disc (CD), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), video capture device, touch screen, stylus, electroacoustic transducer, microphone, speaker, etc) (Col. 5, Ln. 12-23) , wherein the first central processing unit includes an outputter to output, to the second central processing unit, an operation determination signal for determining that the first central processing unit is in operation when a voltage drop in an internal power supply in the first central processing unit is not detected (e.g., Additionally, the hardware management system 300 may automatically shut down and/or reset the information handling system (e.g., to take a processor 312, 314 & 316 of the multi-processor system 310 off-line) when it detects a condition wherein a monitored parameter falls outside of a user-selected threshold or tolerance. For example, upon detecting an out-of-tolerance condition or event, the hardware management system 300 may inform the microcontroller 318 that a specific processor 312, 314 & 316 is to be shut down) (Col. 6, Ln. 35-44, Fig. 6-7), and the processing circuitry selects to stop or not to stop an operation of the second central processing unit when the second central processing unit does not acquire the operation determination signal, and stops the operation of the second central processing unit when the processing circuitry selects to stop the operation of the second central processing unit, and does not stop the operation of the second central processing unit when the processing circuitry selects not to stop the operation of the second central processing unit (e.g., Additionally, the hardware management system 300 may automatically shut down and/or reset the information handling system (e.g., to take a processor 312, 314 & 316 of the multi-processor system 310 off-line) when it detects a condition wherein a monitored parameter falls outside of a user-selected threshold or tolerance. For example, upon detecting an out-of-tolerance condition or event, the hardware management system 300 may inform the microcontroller 318 that a specific processor 312, 314 & 316 is to be shut down. Preferably, the microcontroller 318 is also informed of the time interval to wait before shutting down or resetting the information handling system. The microcontroller 318 may wait for the specified time interval before shutting down or resetting the system. Preferably, the microcontroller 318 may also set a malfunctioning processor's voltage regulator module (VRM) to off so that the processor is taken off-line when the system is reset and restarted. When the information handling system restarts, its system BIOS (Basic Input/Output System) and operating system may automatically operate without the now off-line processor) (Col. 6, Ln. 35-54, also refer to Col 6, Ln. 21-27 which includes “The micro-controller 318 may be coupled to an array of integrated sensors 320,322 & 324 for monitoring key environmental parameters such as processor temperature, fan operation, system voltage, or the like.”). 10. Regarding claim 2 , Spears discloses: The programmable logic controller according to claim 1, wherein the processing circuitry selects to output or not to output, from the first central processing unit to the second central processing unit, an operation stop signal for stopping the operation of the second central processing unit when the voltage drop of the internal power supply in the first central processing unit is detected, and causes the first central processing unit to output the operation stop signal when the processing circuitry selects to output the operation stop signal, and causes the first central processing unit not to output the operation stop signal when the processing circuitry selects not to output the operation stop signal (e.g., For example, aspects of the hardware management system 300 may be implemented as a software application which is executed by one or more of the processors 312, 314 & 316 of the multi-processor system 310. This software may monitor each processor 312, 314 & 316 of the multiprocessor system 310 for proper operation and may perform a shutdown or reset of the system if an out-of-tolerance condition is detected. The hardware management system 300 may also include a processing device such as, for example, a microprocessor or microcontroller 318. The micro-controller 318 may be coupled to an array of integrated sensors 320,322 & 324 for monitoring key environmental parameters such as processor temperature, fan operation, system voltage, or the like.) (Col. 6, Ln. 14-27). 11. Regarding claim 7 , Claim 7 recites a central processing unit capable of controlling a control target device independently of another central processing unit mounted on a programmable logic controller that implement a programmable logic controller of claim 1, with substantially the same limitations, respectively. Therefore the rejection applied to claim 1 also applies to claim 7 respectively. Wherein Spears further teaches A central processing unit capable of controlling a control target device independently of another central processing unit mounted on a programmable logic controller (e.g., For example, aspects of the hardware management system 300 may be implemented as a software application which is executed by one or more of the processors 312, 314 & 316 of the multi-processor system 310. This software may monitor each processor 312, 314 & 316 of the multiprocessor system 310 for proper operation and may perform a shutdown or reset of the system if an out-of-tolerance condition is detected. The hardware management system 300 may also include a processing device such as, for example, a microprocessor or microcontroller 318) (Col. 6, Ln. 14-24, Fig. 5-6). 12. Regarding claim 9 , Claim 9 recites a non-transitory computer-readable recording medium storing a program, the program causing a programmable logic controller including a first central processing unit and a second central processing unit that implement a programmable logic controller of claim 1, with substantially the same limitations, respectively. Therefore the rejection applied to claim 1 also applies to claim 9 respectively. Wherein Spears further teaches A non-transitory computer-readable recording medium storing a program, the program causing a programmable logic controller including a first central processing unit and a second central processing unit mounted on the programmable logic controller to execute processing (e.g., The hardware system 200 is controlled by a central processing system 202. The central processing system 202 includes a central processing unit such as a microprocessor or microcontroller for executing programs, performing data manipulations and controlling the tasks of the hardware system 200. Communication with the central processing system 202 is implemented through a system bus 210 for transferring information among the components of the hardware system 200. The bus 210 may include a data channel for facilitating information transfer between storage and other peripheral components of the hardware system. The bus 210 further provides the set of signals required for communication with the central processing system 202 including a data bus, address bus, and control bus. The bus 210 may comprise any state of the art bus architecture according to promulgated standards, for example industry standard architecture (ISA), extended industry standard architecture (EISA), Micro Channel Architecture (MCA), peripheral component interconnect (PCI) local bus, standards promulgated by the Institute of Electrical and Electronics Engineers (IEEE) including IEEE 488 general-purpose interface bus (GPIB), IEEE 696/S-100, and so on. Other components of the hardware system 200 include main memory 204, auxiliary memory 206, and an auxiliary processing system 208 as required. The main memory 204 provides storage of instructions and data for programs executing on the central processing system 202) (Col. 4, Ln. 9-38) . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Okuma (Pub: 2022/0351797) disclose A computer system 1 shown in FIG. 1 includes a CPU 11, an HDD/SSD 12, a controller 13, and a DRAM 20. The CPU 11 is connected to the HDD/SSD 12 and the DRAM 20 via the controller 13. If a failure occurs in some device in the computer system 1, the entire system stops. To prevent this problem, many systems have a failover function. In an example shown in FIG. 2A, a main system 1A and a backup system 1B are prepared and the main system 1A is operated in normal times. When a failure occurs in a device, for example, the DRAM 20 included in the main system 1A, the main system 1A is stopped and the backup system 1B is operated instead (Para. [0009]). Kawai (Pub: 2021/0243071) disclose a control system and a control method of a multiplexing system (Para. [0001]). Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIGNESHKUMAR C PATEL whose telephone number is (571)270-0698. The examiner can normally be reached Monday - Friday, 7:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth M. Lo can be reached at (571)272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIGNESHKUMAR C PATEL/Primary Examiner, Art Unit 2116 Application/Control Number: 18/724,611 Page 2 Art Unit: 2116 Application/Control Number: 18/724,611 Page 3 Art Unit: 2116 Application/Control Number: 18/724,611 Page 4 Art Unit: 2116 Application/Control Number: 18/724,611 Page 5 Art Unit: 2116 Application/Control Number: 18/724,611 Page 6 Art Unit: 2116 Application/Control Number: 18/724,611 Page 7 Art Unit: 2116 Application/Control Number: 18/724,611 Page 8 Art Unit: 2116 Application/Control Number: 18/724,611 Page 9 Art Unit: 2116 Application/Control Number: 18/724,611 Page 10 Art Unit: 2116
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