DETAILED ACTION
This Office action is in response to the preliminary amendment filed on June 27, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/30/2024 and 03/04/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on June 27, 2024. These drawings are accepted by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by D’Souza et al. (U.S. Pub. No. 2021/0265911 A1).
In re claim 12, D’Souza discloses (Fig. 1) a terminal device (100), comprising:
a boost switch power supply circuit or a buck switch power supply circuit (D’Souza discloses power supply 130 as a boost power supply, but also indicated the power supply 130 can be implemented as a buck power supply as well, Para. 0023);
wherein the boost switch power supply circuit or the buck switch power supply circuit (130) is configured to supply power to a to-be-powered device in the terminal device, and the to-be-powered device comprises a speaker power amplifier (Speaker 120, Para. 0017-0024) or a liquid crystal display (LCD) backlight device.
Allowable Subject Matter
Claims 1-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 1, the prior art of record fails to disclose or suggest “one end of the first inductor is connected to a positive input end of the boost switch power supply circuit, and another end of the first inductor is connected to a first end of the first switch transistor; a second end of the first switch transistor is connected to ground, and a control end of the first switch transistor is connected to a drive signal controller; a first end of the second switch transistor is connected to a public node of the first inductor and the first switch transistor, a second end of the second switch transistor is connected to a positive output end of the boost switch power supply circuit, and a control end of the second switch transistor is connected to the control circuit; the control circuit comprises a first voltage divider circuit and a second voltage divider circuit, and the control circuit outputs a control signal for controlling a switch status of the second switch transistor; the first voltage divider circuit is connected in parallel between the first end of the first switch transistor and the second end of the first switch transistor; the second voltage divider circuit is connected between the second end of the second switch transistor and the ground, the second voltage divider circuit comprises at least two resistors connected in series, a third switch transistor is connected in series between the at least two resistors, a first end of the third switch transistor is connected to the control end of the second switch transistor, and a control end of the third switch transistor is connected to a middle node of the first voltage divider circuit; and the output capacitor is connected in parallel between the positive output end and the ground” in combination with other limitations of the claim. Claims 2-6 depend directly or indirectly from claim 1 and are, therefore, also allowable at least for the same reasons set above.
Regarding to claim 7, the prior art of record fails to disclose or suggest “a first end of the first switch transistor is connected to a positive input end of the buck switch power supply circuit, a second end of the first switch transistor is connected to one end of the first inductor, and a control end of the first switch transistor is connected to a drive signal controller; another end of the first inductor is connected to a positive output end of the buck switch power supply circuit; a first end of the second switch transistor is connected to a first public node of the first switch transistor and the first inductor, a second end of the second switch transistor is connected to ground, and a control end of the second switch transistor is connected to the control circuit; the control circuit comprises a first voltage divider circuit and a second voltage divider circuit, and the control circuit outputs a control signal for controlling a switch status of the second switch transistor; the first voltage divider circuit is connected in parallel between the first end of the second switch transistor and the second end of the second switch transistor; the second voltage divider circuit is connected between the another end of the first inductor and the ground, the second voltage divider circuit comprises at least two resistors connected in series, a third switch transistor is connected in series between the at least two resistors, a first end of the third switch transistor is connected to the control end of the second switch transistor, and a control end of the third switch transistor is connected to a middle node of the first voltage divider circuit; and the output capacitor is connected in parallel between the positive output end and the ground” in combination with other limitations of the claim. Claims 8-11 depend directly or indirectly from claim 7 and are, therefore, also allowable at least for the same reasons set above.
Claims 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 13, the prior art of record fails to disclose or suggest “one end of the first inductor is connected to a positive input end of the boost switch power supply circuit, and another end of the first inductor is connected to a first end of the first switch transistor; a second end of the first switch transistor is connected to ground, and a control end of the first switch transistor is connected to a drive signal controller; a first end of the second switch transistor is connected to a public node of the first inductor and the first switch transistor, a second end of the second switch transistor is connected to a positive output end of the boost switch power supply circuit, and a control end of the second switch transistor is connected to the first control circuit; the first control circuit comprises a first voltage divider circuit and a second voltage divider circuit, and the first control circuit outputs a control signal for controlling a switch status of the second switch transistor; the first voltage divider circuit is connected in parallel between the first end of the first switch transistor and the second end of the first switch transistor; the second voltage divider circuit is connected between the second end of the second switch transistor and the ground, the second voltage divider circuit comprises at least two resistors connected in series, a third switch transistor is connected in series between the at least two resistors, a first end of the third switch transistor is connected to the control end of the second switch transistor, and a control end of the third switch transistor is connected to a middle node of the first voltage divider circuit; and the first output capacitor is connected in parallel between the positive output end and the ground” in combination with other limitations of the claim. Claims 14-16 depend directly or indirectly from claim 13 and are, therefore, also objected at least for the same reasons set above.
Regarding to claim 17, the prior art of record fails to disclose or suggest “a first end of the fourth switch transistor is connected to a positive input end of the buck switch power supply circuit, a second end of the fourth switch transistor is connected to one end of the second inductor, and a control end of the fourth switch transistor is connected to a drive signal controller; another end of the second inductor is connected to a positive output end of the buck switch power supply circuit; a first end of the fifth switch transistor is connected to a first public node of the fourth switch transistor and the second inductor, a second end of the fifth switch transistor is connected to ground, and a control end of the fifth switch transistor is connected to the second control circuit; the second control circuit comprises a third voltage divider circuit and a fourth voltage divider circuit, and the second control circuit outputs a control signal for controlling a switch status of the fifth switch transistor; the third voltage divider circuit is connected in parallel between the first end of the fifth switch transistor and the second end of the fifth switch transistor; the fourth voltage divider circuit is connected between the another end of the second inductor and the ground, the fourth voltage divider circuit comprises at least two resistors connected in series, a sixth switch transistor is connected in series between the at least two resistors, a first end of the sixth switch transistor is connected to the control end of the fifth switch transistor, and a control end of the sixth switch transistor is connected to a middle node of the third voltage divider circuit; and the second output capacitor is connected in parallel between the positive output end and the ground” in combination with other limitations of the claim. Claims 18-20 depend directly or indirectly from claim 17 and are, therefore, also objected at least for the same reasons set above.
Conclusion
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838