DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OMORI et al. (2021/0351813).
As to claim 1, OMORI et al. (hereinafter OMORI) discloses a network inspection system and computer readable medium comprising a signal output circuit (212, Fig. 2, [0067]) configured to output a first digital signal (selected network) consisting of one bit representing a waveform of a predetermined pattern or a signal based on the first digital signal to a transmission line as a measurement signal (basic signal 111, Fig. 4, [0093], [0095]); a signal reception circuit (AD conversion unit 284, Fig. 2, [0050]) configured to receive a response signal (112, Fig. 4) including a signal reflecting the measurement signal [0049] from the transmission line and convert the response signal into a second digital signal consisting of one bit; an operation circuit (221, Fig. 2, [0051], [0052]) configured to perform a logical operation of the second digital signal converted by the signal reception circuit and a third digital signal consisting of one bit based on the predetermined pattern (113, Fig. 4); and a detection circuit (221), [0053] – [0055] configured to detect an abnormality of the transmission line, based on an operation result obtained by the operation circuit (Fig. 1, 2 and 4).
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As to claim 8, OMORI et al. (hereinafter OMORI) discloses a network inspection system and computer readable medium comprising of one bit representing a waveform of a predetermined pattern (212, Fig. 2, [0067]) or a signal based on the first digital signal to a transmission line as a measurement signal (basic signal 111, Fig. 4, [0093], [0095]); receiving a response signal (AD conversion unit 284, Fig. 2, [0050]) including a signal reflecting the measurement signal [0039] from the transmission line and converting the response signal into a second digital signal consisting of one bit; performing a logical operation (221, Fig. 2, [0051], [0052]) of the converted second digital signal and a third digital signal consisting of one bit based on the predetermined pattern (113, Fig. 4); and detecting (221), [0053] – [0055] an abnormality of the transmission line, based on an operation result (Fig. 1, 2 and 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over OMORI et al. (2021/0351813).
As to claim 2, OMORI discloses an operation circuit (221, Fig. 2, [0041], [0042])). OMORI fails to explicitly to calculate an exclusive OR of the second digital signal and the third digital signal. However, OMORI discloses a processing circuit (209), (Fig. 20) capable of using a logical calculation such as exclusive OR when comparing digital data would be within the level of one of ordinary skill in the art. Therefore, at the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to calculate an exclusive OR of the second digital signal and the third digital signal to stabilize the signal.
As to claims 5 and 12, OMORI discloses that the operation circuit ((221, Fig. 2, [0041], [0042])) includes an adjustment circuit (286) configured to perform phase adjustment (Fig. 8 and 9). OMORI fails to explicitly disclose an adjustment circuit configured to perform phase adjustment that of the second digital signal and the third digital signal. However, at the time of the invention, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to perform phase adjustment of the second digital signal and the third digital signal using the adjustment circuit so as to match each other as required by the processing circuit.
Allowable Subject Matter
Claims 3 – 4, 6 – 7, 9 – 11 and 13 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior Art of Record
The prior art made of record and not relied upon is considered pertinent to applicant s disclosure.
Sakurazawa et al. (11,979,482) is cited for its disclosure of a detection system, detection device and detection method.
CABANILLAS et al. (20200116777) is cited for its disclosure of a system for detecting faults in a transmission line by using a complex signal.
Yang et al. (12,282,052) is cited for its disclosure of a bus authentication and anti-probing architecture.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to REENA AURORA whose telephone number is (571)272-2263. The examiner can normally be reached M-F: 8:00AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at 5712705628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/REENA AURORA/Primary Examiner, Art Unit 2858