DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kenichi (JP2014046493A, cited in IDS).
As to claim 1, Kenichi discloses a printed wiring board (fig. 1) comprising:
a base material 11 having a main surface;
a conductive pattern 121 that is disposed on the main surface; and
a plating layer 122, 123, wherein a through hole 113 is formed in the base material, the through hole extending through the base material in a thickness direction,
a thickness of the base material is 0.5 mm or more (¶0014 discloses a thickness of 0.6mm),
the plating layer is disposed on at least an inner wall surface of the through hole and electrically connected to a portion of the conductive pattern around the through hole (fig. 1), and
a thickness of the plating layer on the inner wall surface of the through hole is greater than a thickness of the conductive pattern and 10 µm or more (¶0032 discloses conductive pattern 121 having a thickness of 1 µm to 5 µm; ¶0041 discloses that the average thickness of the electroless plating layer 122 may be a thickness of about 0.1 µm to 1 µm; ¶0043, metal layer 123 has a thickness in the rage of 1 to 100µm).
As to claim 2, Kenichi wherein the base material includes a dielectric layer, the main surface is a front surface of the dielectric layer, the dielectric layer includes fluororesin (¶0014) and filler that is mixed in the fluororesin (¶0018-0019), and the filler is formed by using silica.
As to claim 3, Kenichi discloses that a shape of the filler is spherical (¶0019).
As to claim 5, Kenichi discloses that the thickness of the plating layer on the inner wall surface of the through hole is 20 µm or more (¶0041 discloses that the average thickness of the electroless plating layer 122 may be a thickness of about 0.1 µm to 1 µm; ¶0043, metal layer 123 has a thickness in the rage of 1 to 100µm).
As to claim 6, Kenichi discloses that the thickness of the plating layer on the inner wall surface of the through hole is 30 µm or more (¶0041 discloses that the average thickness of the electroless plating layer 122 may be a thickness of about 0.1 µm to 1 µm; ¶0043, metal layer 123 has a thickness in the rage of 1 to 100µm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kenichi (JP2014046493A, cited in IDS).
As to claim 4, Kenichi discloses that a portion of the dielectric layer is included in the inner wall surface of the through hole (figs. 1, 4-8).
However, Kenichi does not disclose that an atomic ratio of silicon on a portion of the dielectric layer included in the inner wall surface of the through hole is 5% or more and 60% or less.
Kenichi discloses using a filler in the resin such as silica and the content being 20% mass or more and 80% mass or less (¶0018-0019). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric layer included in the inner wall of Kenichi have an atomic ratio of Silicon be 5% or more and 60% or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kenichi (JP2014046493A, cited in IDS) in view of Watanabe (Pub. No. US 2002/0023778).
As to claim 7, Kenichi discloses that the plating layer includes an underlying conductive layer 122 and a plating layer 123 that is disposed on the underlying conductive layer, the plating layer is further disposed on the portion of the conductive pattern around the through hole.
However, Kenichi does not disclose that the plating layer is an electrolytic plating layer; the underlying conductive layer and the electrolytic plating layer form a step on the portion of the conductive pattern around the through hole.
Watanabe discloses that an underlying conductive layer and an electrolytic plating layer form a step on the portion of the conductive pattern around the through hole (fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the underlying conductive layer and the electrolytic plating layer form a step on the portion of the conductive pattern around the through hole in order to reduce the thickness and size of the wiring layer around the through hole.
It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to have the plating layer be made with an electrolytic process, since it has been held by the courts that patentability of a product does not depend on its method of production. If the product in the product-by-process claim is disclosed, or suggested, by the Prior Art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966 (Fed. Cir. 1985).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMOL H PATEL whose telephone number is (571)270-7833. The examiner can normally be reached 9:30AM-6:00PM.
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/AMOL H PATEL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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