DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9, 12 & 16-25 (Total of 20 claims) have been presented and pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9, 12 & 16-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1;
In line 2, it is unclear and unstated as to who or what performs/supports the “receive a data packet” step function.
In line 4, it is unclear and unstated as to who or what performs/supports the “determining” step function.
In line 8, it is unclear and unstated as to who or what performs/supports the “distributing” step function.
In line 10 it is unclear and unstated as to who or what performs/supports the “transmitting” step function.
Claim 6;
In line 8, “same as local chip identification information” lacks functional, proper and clear antecedent basis (i.e., it is unclear as to how & whether the “local chip identification information” is interconnected to the rest of the claimed recitations such as the “chip identification information”. How is the chip id functionally/structurally related to the local chip id?). The unclarities of the claim 1 are similarly applied.
Claim 12,
The unclarities of the claim 1 are similarly applied; in addition, it is unclear as to whether the single “processor” of the line 2 performs the functions of lines 7-end (i.e., which of the specification & drawing supports/represents the claimed single “processor performing all the recited functions”?).
Allowable Subject Matter
Claims 3-4, 7-9, 16-18, 20-21 & 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten, to overcome all the pending rejections, in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 6, 12, 19, 22 & 25 are rejected under 35 U.S.C. 103 as being unpatentable over Fang (US 2018/0052793 A1).
The examiner relies on the entire teachings of the Fang reference; the examiner advises the applicant to carefully consider the entire teachings of the Fang reference to better understand the examiner position and the interpretations of the claimed invention.
As for the independent claims 1, 6 & 12, the Fang reference teaches, when the examiner applies Broadest Reasonable Interpretation, functionally equivalent teachings of the claimed invention as follows:
CLAIMS 1, 6 & 12
Fang Ref. Teachings (emphasis added/underlined)
1.(Original) A data transmission method, comprising: receiving a data packet to be transmitted, the data packet to be transmitted comprising data to be transmitted and chip identification information;
Fig 2, (222 & 230); par 76, “apparatus 223 may receiving …enumeration instruction that is sent by the management BMC…when performing device enumeration, the internal processing apparatus 223 may send multiple configuration read/write packets to the at least one PCIe downstream port 222… carries a request identification (RID) & a CID”,
determining a target first peripheral component interconnect express (PCIE) physical layer port corresponding to the chip identification information from a plurality of first PCIE physical layer ports,
par 76, “the value the RID may be set to a BDF of the internal processing apparatus 223, and a value of the CID may be numbered in sequence starting from an initial value”
the plurality of first PCIE physical layer ports and a plurality of chips being interconnected one to one;
par 70-71, “PCIe upstream ports 221 may be connected to the N1 hosts 210 in a one-to-one correspondence…PCIe downstream ports 222 may be connected to the M1 I/O devices 230 in one-to-one correspondence”
distributing the data packet to be transmitted to the target first PCIE physical layer port; and
par 76, “when performing device enumeration, the internal processing apparatus 223 may send multiple configuration read/write packets to the at least one PCIe downstream port 222… carries a request identification (RID) & a CID”
transmitting the data packet to be transmitted to a receiving chip through the target first PCIE physical layer port, the receiving chip being a chip interconnected with the target first PCIE physical layer port.
Obvious from the Par 82, “a data packet sent by the M1 I/O devices 230 using the M2 PCIe downstream ports 222, process the received data packet”, see also par 94, “forwarding processing on a data packet transmitted between the N1 hosts 210 and the N1 I/O devices 230”; the examiner notes that the claimed “chip” is not expressly taught, but the I/O devices 230 teaches the claimed “chip” function
6. (Original) A data transmission method, comprising: receiving a data packet to be transmitted by a target second PCIE physical layer port, the target second PCIE physical layer port being a port interconnected with a transmitting chip in a plurality of second PCIE physical layer ports,
Fig 2, (222 & 230); par 76, “send multiple configuration read/write packets to the at least one PCIe downstream port 222. The configuration read/write packets carry a request identification (RID) and a CID, where a value of the RID may be set to a BDF…a value of CID may be numbered in sequence starting from an initial value”; the examiner notes that the sent packet is received by 222, which teaches the claimed invention. See also, the Par 76, “The configuration read/write response packet carries a RID and CID in the corresponding configuration read/write packet…whether the switching device 220 is connected to a physical device whose BDF number is the CUD in the configuration read/write response packet”
the plurality of second PCIE physical layer ports and a plurality of chips being interconnected one to one,
par 70-71, “PCIe upstream ports 221 may be connected to the N1 hosts 210 in a one-to-one correspondence…PCIe downstream ports 222 may be connected to the M1 I/O devices 230 in one-to-one correspondence”
the data packet to be transmitted comprising data to be transmitted and chip identification information; and
Fig 2, (222 & 230); Par 76, “The configuration read/write response packet carries a RID and CID in the corresponding configuration read/write packet…whether the switching device 220 is connected to a physical device whose BDF number is the CID in the configuration read/write response packet”
in response to determining that the chip identification information is the same as local chip identification information, transmitting the data packet to be transmitted to a local user layer.
Par 76, “recognizing the CID in the configuration read/write response packet), whether the switching device 220 is connected to a physical device whose BDF number is the CID in the configuration read/write response packet”
12. (Currently Amended) A data transmission device, comprising: a processor; and a memory for storing executable instructions; wherein the processor is configured to read the executable instructions from the memory and execute the executable instructions to perform:
Inherent/obvious features of figure 2 operations/functions
receiving a data packet to be transmitted, the data packet to be transmitted comprising data to be transmitted and chip identification information;
par 76, “apparatus 223 may receiving …enumeration instruction that is sent by the management BMC…when performing device enumeration, the internal processing apparatus 223 may send multiple configuration read/write packets to the at least one PCIe downstream port 222… carries a request identification (RID) & a CID”
determining a target first peripheral component interconnect express (PCIE) physical layer port corresponding to the chip identification information from a plurality of first PCIE physical layer ports,
par 76, “the value the RID may be set to a BDF of the internal processing apparatus 223, and a value of the CID may be numbered in sequence starting from an initial value”
the plurality of first PCIE physical layer ports and a plurality of chips being interconnected one to one;
par 70-71, “PCIe upstream ports 221 may be connected to the N1 hosts 210 in a one-to-one correspondence…PCIe downstream ports 222 may be connected to the M1 I/O devices 230 in one-to-one correspondence”
distributing the data packet to be transmitted to the target first PCIE physical layer port; and
par 76, “when performing device enumeration, the internal processing apparatus 223 may send multiple configuration read/write packets to the at least one PCIe downstream port 222… carries a request identification (RID) & a CID”
transmitting the data packet to be transmitted to a receiving chip through the target first PCIE physical layer port, the receiving chip being a chip interconnected with the target first PCIE physical layer port.
Obvious from the Par 82, “a data packet sent by the M1 I/O devices 230 using the M2 PCIe downstream ports 222, process the received data packet”, see also par 94, “forwarding processing on a data packet transmitted between the N1 hosts 210 and the N1 I/O devices 230”; the examiner notes that the claimed “chip” is not expressly taught, but the I/O devices 230 teaches the claimed “chip” function
The examiner notes that the above discussed teachings of data transmission method of the Fang reference uses/labels “PCIe downstream port” for receiving and/or transmitting data rather than the claimed “PCIE physical layer port”; similarly, the Fang reference does not expressly uses/labels the claimed “chip” (i.e., the Fang reference teaches I/O device) for receiving and/or transmitting data.
In other words, the claimed data transmission appears to be performed in a slightly different environment types (i.e., the downstream port instead of the physical layer port & the device instead of the chip).
However, as can be seen from the claimed recitations, the functional equivalence teachings of the recited claimed environment & the data transmission function of the PCIE physical layer port are for reliably transmitting and/or receiving data (i.e., “data transmission”), and that the Fang reference clearly teaches the functionally equivalent limitations (i.e., the data transmission) of the above discussed not expressly discussed differences.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to come up with the claimed invention from the functionally equivalent teachings of the Fang reference for the above reasons and the detailed teachings discussed above.
As for the dependent claims 2, 5, 19, 22 & 25, further adds limitations as follow:
CLAIMS 2, 5, 19, 22 & 25
Fang Ref. Teachings (emphasis added/underlined)
2. (Currently Amended) The method according to claim 1, wherein distributing the data packet to be transmitted to the target first PCJE physical layer port comprises: distributing the data packet to be transmitted to the target first PCJE physical layer port according to the chip identification information.
Obvious from the teachings of par 76, “when performing device enumeration, the internal processing apparatus 223 may send multiple configuration read/write packets to the at least one PCIe downstream port 222… carries a request identification (RID) & a CID”
5. (Currently Amended) The method according to claim 1, further comprising: detecting respectively an error on physical links of the plurality of first PCIE physical layer ports; and in response to detecting an error on a physical link of any PCIE physical layer port, correcting an error-prone physical link into an error-free data link.
Obvious from the teachings of par 78, “when… the PCIe system 200 is faulty, only at least on host 210 and at least one I/O device 230 that are connected…are affected, and another switching device, and host and 210 an I/O device 230 that are connected to the other switching device in the PCIe system 200 are not affected…reliability of the PCIe system 200 can be improved”; the examiner also notes that error correction is highly motivated, well-known and commonly practiced in the art.
19. (New) The data transmission device according to claim 12, wherein distributing the data packet to be transmitted to the target first PCIE physical layer port comprises: distributing the data packet to be transmitted to the target first PCIE physical layer port according to the chip identification information.
The teachings of the claim 2 are similarly applied.
22. (New) The data transmission device according to claim 12, wherein the processor is further configured to read the executable instructions from the memory and execute the executable instructions to perform: detecting respectively an error on physical links of the plurality of first PCIE physical layer ports; and in response to detecting an error on a physical link of any PCIE physical layer port, correcting an error-prone physical link into an error-free data link.
The teachings of the claim 5 are similarly applied
25. (New) A data transmission device, comprising: a processor; and a memory for storing executable instructions; wherein the processor is configured to read the executable instructions from the memory and execute the executable instructions to perform the method of claim 6.
Inherent/obvious features of figure 2 operations.
As can be seen from the above discussed functionally equivalent and/or obvious teachings of the further added limitations of the dependent claims, the Fang reference further teaches the obvious reasons of the further added limitations of the claimed invention. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to come up with the claimed invention from the functionally equivalent teachings of the Fang reference for the above obvious reasons and the detailed teachings discussed above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181