DETAILED ACTION
Response to Amendment
The Applicant’s Amendment, filed 11/12/2025 has been entered. Claims 16-30 are pending in the Application.
Response to Arguments
Applicant’s arguments with respect to the prior art rejection have been considered but are moot upon further consideration and a new ground of rejection under 35 U.S.C. 103 as being unpatentable over Kopp US 20130064321, in view of Wise et al US 20220327091 and in view of Aue et al US 20140359179.
Regarding claims 16 and 18, the Applicant argues that the cited arts fail to teach the newly amended limitation “wherein the master data processing unit and the slave data processing unit are both SPI devices”. However, the newly cited Wise et al (US 20220327091) discloses a master and a slave device both having multi-protocol interfaces that can act as either SPI devices or UART devices (see figures 3 and 10, chip 106 and module 108, see para 0029 and 0032, When the interface is operating in data transfer mode, the first device and the second device may be configured to perform an SPI data transfer). Therefore, it would have been obvious to modify the device of Kopp and incorporate multi-protocol interfaces that capable to act as either a SPI and/or UART devices. The motivation for doing so is to provide greater flexibility in communication by using different communication protocols.
Based on the reasoning above, the rejections have been modified to address the newly amended limitation. Please see below for the detailed rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-18, 23-25 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kopp US 20130064321, in view of Wise et al US 20220327091 and in view of Aue et al US 20140359179.
Regarding claim 16, Kopp teaches a communication method for a communication network (see figure 1), wherein the network comprises: a master data processing unit (data transmission device 10), and a slave data processing unit (data receiving device 20) communicatively coupled via a synchronous serial communication interface (SPI interface 11), and via a slave select line (slave select line 14) for indicating that data is being sent from the master data processing unit to the slave data processing unit (see para 0024, two control lines 13 and 14 of this SPI interface 10 are shown that correspond to the clock line CLK and to the slave select (SS), also called chip select (CS)), the method comprising:
sending data from the master data processing unit to the slave data processing unit and/or from the slave data processing unit to the master data processing unit, wherein the sent data is framed by a start bit as a first bit and a stop bit as a last bit (see para 0028, The two data words Z1 and Z are subsequently supplemented by linking with a bit mask M with two frame bits, one start bit SO and one stop bit P1 so that the data word E1 or E to be transmitted is present in the asynchronous serial UART data format, whereby the bit value of the start bit SO always has the value 0 and the bit value of the start bit P1 always has the value 1, also see para 0029, This data word E1 or E is shifted into the shift register 11 a from which as transmitting register of the SPI interface 11 this data word is serially read out in the transmitter bit timing of the SPI interface for transmission via the data line 12 to the UART interface 21 of the microcomputer 20).
But Kopp fails to teach the master data processing unit and the slave data processing unit are both SPI devices. In Kopp, the master is a SPI device while the slave is an UART device.
However, Wise teaches a master and a slave device both having multi-protocol interfaces that can act as either SPI devices or UART devices (see figures 3 and 10, chip 106 and module 108, see para 0029 and 0032, When the interface is operating in data transfer mode, the first device and the second device may be configured to perform an SPI data transfer).
Therefore, it would have been obvious to modify the device of Kopp and incorporate multi-protocol interfaces that capable to act as either a SPI and/or UART devices.
The motivation for doing so is to provide greater flexibility in communication by using different communication protocols.
The combination of Kopp and Wise fails to teach a communication network of a vehicle.
However, Aue teaches a serial communication network implemented for a vehicle (see the abstract, a microcontroller for a control unit, in particular for a vehicle control unit… The microcontroller is configurable in such a way that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill functions corresponding to one of multiple serial interfaces, in particular of SPI, UART, LIN, CAN, PSI5, FlexRay, SENT, IC2, MSC or Ethernet).
Therefore, it would have been obvious to modify the communication network of Kopp and further incorporating the network in a vehicle.
The motivation for doing so is to utilize the communication network in different applications such as in a vehicle control system.
Regarding claim 17, Kopp further teaches the slave data processing unit is connected to the master data processing unit via: a serial clock line for synchronizing a sampling time of the master data processing unit and a sampling time of the slave data processing unit (clock line 13), and a master-out-slave-in data line for data output from the master data processing unit to the slave data processing unit (MOSI line 12), the method further comprising: indicating that the data is being sent from the master data processing unit to the slave data processing unit using the slave select line; synchronizing the sampling time of the master data processing unit to the sampling time of the slave data processing unit using the serial clock line after and/or during indicating that the data is being sent from the master data processing unit to the slave data processing unit, and sending the data from the master data processing unit to the slave data processing unit using the master-out-slave-in data line after and/or during synchronizing the sampling time of the master data processing unit to the sampling time of the slave data processing unit (see para 0024, The SPI interface 11 comprises in the simplest case at least one shift register 11 a as transmitting register and has a data output MOSI (also called serial data output (SDO)) connected to the data line 12, whereby the customarily provided data input MISO for the second data line is not shown. Furthermore, two control lines 13 and 14 of this SPI interface 10 are shown that correspond to the clock line CLK and to the slave select (SS), also called chip select (CS)).
Regarding claim 18, Kopp further teaches the slave data processing unit is connected to the master data processing unit via a master-in-slave-out data line for data output from the slave data processing unit to the master data processing unit, the method further comprising: sending the data from the slave data processing unit to the master data processing unit using the master-in-slave-out data line after and/or during synchronizing the sampling time of the master data processing unit to the sampling time of the slave data processing unit (see para 0005, a serial data transfer, e.g., according to the SPI protocol, takes place via three lines, namely, via a transmitting line (MOSI), a receiving line (MISO) and a clock line (SCLK)).
Regarding claim 23, Kopp teaches a communication network (see figure 1), comprising:
a master data processing unit (data transmission device 10); and
a slave data processing unit (data receiving device 20)
wherein the master data processing unit and the slave data processing unit are communicatively coupled via a synchronous serial communication interface (SPI interface 11) and via a slave select line (slave select line 14) for indicating that data is being sent from the master data processing unit to the slave data processing unit (see para 0024, two control lines 13 and 14 of this SPI interface 10 are shown that correspond to the clock line CLK and to the slave select (SS), also called chip select (CS)), and
wherein the master data processing unit is configured to frame the data sent from the master data processing unit to the slave data processing unit with a start bit as a first bit and a stop bit as a last bit of the sent data, and/or the slave data processing unit is configured to frame the data sent from the slave data processing unit to the master data processing unit with a start bit as a first bit and a stop bit as a last bit of the sent data (see para 0028, The two data words Z1 and Z are subsequently supplemented by linking with a bit mask M with two frame bits, one start bit SO and one stop bit P1 so that the data word E1 or E to be transmitted is present in the asynchronous serial UART data format, whereby the bit value of the start bit SO always has the value 0 and the bit value of the start bit P1 always has the value 1, also see para 0029, This data word E1 or E is shifted into the shift register 11 a from which as transmitting register of the SPI interface 11 this data word is serially read out in the transmitter bit timing of the SPI interface for transmission via the data line 12 to the UART interface 21 of the microcomputer 20).
But Kopp fails to teach the master data processing unit and the slave data processing unit are both SPI devices. In Kopp, the master is a SPI device while the slave is an UART device.
However, Wise teaches a master and a slave device both having multi-protocol interfaces that can act as either SPI devices or UART devices (see figures 3 and 10, chip 106 and module 108, see para 0029 and 0032, When the interface is operating in data transfer mode, the first device and the second device may be configured to perform an SPI data transfer).
Therefore, it would have been obvious to modify the device of Kopp and incorporate multi-protocol interfaces that capable to act as either a SPI and/or UART devices.
The motivation for doing so is to provide greater flexibility in communication by using different communication protocols.
The combination of Kopp and Wise fails to teach a communication network of a vehicle.
However, Aue teaches a serial communication network implemented for a vehicle (see the abstract, a microcontroller for a control unit, in particular for a vehicle control unit… The microcontroller is configurable in such a way that the at least one interface-unspecific input module, the at least one interface-unspecific output module, the at least one routing unit and the at least one arithmetic unit for processing interface-specific information fulfill functions corresponding to one of multiple serial interfaces, in particular of SPI, UART, LIN, CAN, PSI5, FlexRay, SENT, IC2, MSC or Ethernet).
Therefore, it would have been obvious to modify the communication network of Kopp and further incorporating the network in a vehicle.
The motivation for doing so is to utilize the communication network in different applications such as in a vehicle control system.
Regarding claims 24-25, please refer to the rejection of claims 17-18 above since the claimed subject matter is substantially similar.
Regarding claim 30, Aue further teaches a vehicle, comprising: the communication network (see para 0023, control units in a vehicle customarily have serial interfaces such as SPI, UART, LIN, CAN, PSI5, FlexRay, SENT, Ethernet, I2C, MSC (Micro Second Channel) and others for connecting to or communicating with other control units).
Claims 19-22, and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Kopp, Wise and Aue as applied to claims above, and further in view of Ongyanco US 20220075754.
Regarding claim 19, the combination of Kopp, Wise and Aue teaches all the features with respect to claim 16 as outlined above.
But, the combination of Kopp, Wise and Aue fails to teach the network comprises: a monitoring data processing unit comprising an asynchronous serial communication interface, wherein the monitoring data processing unit is connected via the asynchronous serial communication interface to the master data processing unit and the slave data processing unit, and wherein the monitoring data processing unit recognizes a beginning of the sent data using the start bit and an end of the sent data using the stop bit.
However, Ongyanco teaches a monitoring data processing unit comprising an asynchronous serial communication interface (see figure 4, controller 406 having monitor interfaces 412 and 414, see para 0048, connected via a serial peripheral interface (SPI) bus, a controller area network (CAN) bus, a universal asynchronous receiver-transmitter (UART) bus, etc ), wherein the monitoring data processing unit is connected via the asynchronous serial communication interface to the master data processing unit and the slave data processing unit (see figure 4 shows connection of controller 406 to master 402 and slave 404), and wherein the monitoring data processing unit recognizes a beginning of the sent data using the start bit and an end of the sent data using the stop bit (see para 0054, The controller may be configured to interpret the message by determining at least one of a start bit, an address, an acknowledgment, a negative acknowledgment, a data value, and a stop bit of the serial communication. The controller may be configured to obtain the data value from the interpreted message and to perform the control function according to the obtained data value).
Therefore, it would have been obvious to modify the communication network of Kopp and further incorporating the network monitoring unit of Ongyanco.
The motivation for doing so is to provide data monitoring for the communication network thus enhancing its functionality.
Regarding claim 20, Ongyanco further teaches the monitoring data processing unit is connected to a master-out-slave-in data line (see para 0046, Although FIG. 4 illustrates the lines 408 and 410 as I2C serial clock and data lines, in other embodiments the lines 408 and 410 may be other suitable serial communication lines. For example, the master electronic device 402 and the slave electronic device 404 may be connected via a serial peripheral interface (SPI) bus, a controller area network (CAN) bus, a universal asynchronous receiver-transmitter (UART) bus, etc. the MOSI lines in SPI bus), and
wherein the monitoring data processing unit recognizes the beginning of the data sent from the master data processing unit to the slave data processing unit via the master-out-slave-in data line using the start bit and the end of the data sent from the master data processing unit to the slave data processing unit via the master-out-slave-in data line using the stop bit (see para 0054, The controller may be configured to interpret the message by determining at least one of a start bit, an address, an acknowledgment, a negative acknowledgment, a data value, and a stop bit of the serial communication. The controller may be configured to obtain the data value from the interpreted message and to perform the control function according to the obtained data value).
Regarding claim 21, Ongyanco further teaches the monitoring data processing unit is connected to a master-in-slave-out data line (see para 0046, Although FIG. 4 illustrates the lines 408 and 410 as I2C serial clock and data lines, in other embodiments the lines 408 and 410 may be other suitable serial communication lines. For example, the master electronic device 402 and the slave electronic device 404 may be connected via a serial peripheral interface (SPI) bus, a controller area network (CAN) bus, a universal asynchronous receiver-transmitter (UART) bus, etc. the MISO lines in SPI bus), and
wherein the monitoring data processing unit recognizes the beginning of the data sent from the slave data processing unit to the master data processing unit via the master-in-slave-out data line using the start bit and the end of the data sent from the slave data processing unit to the master data processing unit via the master-in-slave-out data line using the stop bit (see para 0054, The controller may be configured to interpret the message by determining at least one of a start bit, an address, an acknowledgment, a negative acknowledgment, a data value, and a stop bit of the serial communication. The controller may be configured to obtain the data value from the interpreted message and to perform the control function according to the obtained data value).
Regarding claim 22, Ongyanco further teaches the monitoring data processing unit samples the received data with the same sampling time as the master data processing unit and the slave data processing unit (see para 0056, monitoring the serial communication may not introduce a delay to the serial communication).
Regarding claims 26-29, please refer to the rejection of claims 19-22 since the claimed subject matter is substantially similar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhong et al US 20190391935 discloses a SPI master and slave devices capable of communicating using both SPI and UART protocols.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHONG H DANG/ Primary Examiner, Art Unit 2184