Prosecution Insights
Last updated: August 06, 2026
Application No. 18/725,761

MULTILAYER CERAMIC CAPACITOR

Final Rejection §102§103
Filed
Jun 29, 2024
Priority
Dec 29, 2021 — RE 10-2021-0190663 +2 more
Examiner
RAMASWAMY, ARUN
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Amotech Co., Ltd.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
680 granted / 804 resolved
+16.6% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
19 currently pending
Career history
838
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
59.8%
+19.8% vs TC avg
§102
29.4%
-10.6% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 804 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1 and its depending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 3, and 6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang et al. (US Publication 2019/0237252). In re claim 1, Jang discloses a multilayer ceramic capacitor comprising: a ceramic body (110, 210 – Figure 2, Figure 3, ¶23) in which a plurality of dielectric layers (Figure 2, Figure 3; Note that the substrate can be divided into an arbitrary number of layers.) are stacked; a lower electrode (121, 122 on 110 – Figure 2, ¶23) formed on a lower surface of the ceramic body (Figure 2, Figure 3; Note that the Examiner is taking the top surface of 110 to be the ‘lower surface’.); and an electrode pole (121 in T1, 122 in T2 – Figure 2, ¶23) formed from the lower surface of the ceramic body (110 – Figure 2) toward an inner center of the ceramic body (Figure 2), wherein the lower electrode comprises a first lower electrode (121 – Figure 2) and a second lower electrode (122 – Figure 2) formed on both sides of the lower surface of the ceramic body (Figure 2), and wherein the electrode pole comprises: a first electrode pole (121 in T1 – Figure 2) formed on one side of the lower surface of the ceramic body (110 – Figure 2) and electrically connected to the first lower electrode (121 – Figure 2); and a second electrode pole (122 in T2 – Figure 2) formed on the other side of the lower surface of the ceramic body (110 – Figure 2) and electrically connected to the second lower electrode (122 – Figure 2), wherein the first electrode pole (121 in T1 – Figure 2) and the second electrode pole (122 in T2 – Figure 2) are disposed to be spaced apart from each other such that length directions thereof are parallel to a height direction of the ceramic body (Figure 2), and wherein no inner electrode is disposed inside the ceramic body (Figure 2), and the first electrode pole (121 in T1 – Figure 2) and the second electrode pole (122 in T2 – Figure 2) are configured to function as electrodes to form capacitance therebetween (¶31). In re claim 3, Jang discloses the multilayer ceramic capacitor of claim 1, as explained above. Jang further discloses wherein the first electrode pole (121 in T1 – Figure 2) and the second electrode pole (122 in T2 – Figure 2) are formed to face each other at a location symmetrical to the lower surface of the ceramic body (top surface of 110 – Figure 2). In re claim 6, Jang discloses the multilayer ceramic capacitor of claim 1, as explained above. Jang further discloses wherein the electrode pole (121 in T1, 122 in T2 – Figure 2) is provided with a metal layer (131, 132 – Figure 2, ¶46) on a surface thereof (Figure 2; Note that elements 131 and 132 are ‘on’ the electrode poles despite not directly contacting them.). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US Publication 2019/0237252) in view of Fukudome et al. (US Publication 2008/0043400). In re claim 4, Jang discloses the multilayer ceramic capacitor of claim 1, as explained above. Jang further discloses the electrode poles (221 in 251, 222 in 252 – Figure 3, ¶52) can fully penetrate the ceramic substrate (210 – Figure 3, ¶51). Jang does not disclose wherein a diameter of a cross section that is vertical to the length direction of the electrode pole is reduced toward an inner center of the ceramic body. Fukudome discloses wherein a diameter of a cross section that is vertical to the length direction of the electrode pole (47 – Figure 2, Figure 5, ¶74) is reduced toward an inner center of the ceramic body (18 – Figure 2, ¶50, Abstract). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the tapered conductors to suppress the amount of ringing (¶94: Fukudome). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US Publication 2019/0237252) in view of Masuda et al. (US Publication 2009/0154054). In re claim 5, Jang discloses the multilayer ceramic capacitor of claim 3, as explained above. Jang does not disclose wherein a plurality of first electrode poles are disposed along a length direction of the first lower electrode, and wherein a plurality of second electrode poles are disposed along a length direction of the second lower electrode, and the second electrode poles maintain the same interval as the interval of the first electrode poles, respectively. Masuda discloses a plurality of first electrode poles (18 – Figure 1, ¶26) are disposed along a length direction of the first lower electrode (16 – Figure 1, ¶26), and wherein a plurality of second electrode poles (22 – Figure 1, ¶26) are disposed along a length direction of the second lower electrode (20 – Figure 1, ¶26), and the second electrode poles maintain the same interval as the interval of the first electrode poles, respectively (Figure 3; Note that the poles are evenly spaced.). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the plurality of electrode poles as described by Masuda to increase the capacitance of the device (¶26: Masuda). Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al. (US Publication 2019/0237252). In re claim 7, Jang discloses the multilayer ceramic capacitor of claim 1, as explained above. Jang does not explicitly disclose the electrode pole is formed with a length that is equal to or smaller than a half of a height of the ceramic body. However, Jang discloses the depth of the trench, or electrode pole, is correlated to the capacitance of the device (¶31, ¶53, ¶67). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the length of the electrode pole to achieve a device having desired capacitance, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jang et al. (US Publication 2019/0237251) Figure 2, Figure 3 Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ARUN RAMASWAMY/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jun 29, 2024
Application Filed
Jan 09, 2026
Non-Final Rejection mailed — §102, §103
Mar 27, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12700544
MULTILAYER CERAMIC CAPACITOR
3y 4m to grant Granted Aug 04, 2026
Patent 12700542
MULTILAYER ELECTRONIC COMPONENT
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Patent 12700540
MULTILAYER CERAMIC ELECTRONIC COMPONENT
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Patent 12700545
MULTILAYER ELECTRONIC COMPONENT
1y 2m to grant Granted Aug 04, 2026
Patent 12695028
INNER ELECTRODE MATERIAL FOR MULTILAYERED CAPACITOR AND MULTILAYERED CAPACITOR COMPRISING THE SAME
2y 4m to grant Granted Jul 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
97%
With Interview (+12.4%)
2y 6m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 804 resolved cases by this examiner. Grant probability derived from career allowance rate.

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